chipsalliance/f4pga-examples

Symbiflow-classroom: Parameterizing top-level module

nelsobe opened this issue · 3 comments

SYMBIFLOW-CLASSROOM-PROJECT

If a top-level module in a design has a parameter associated with it, is there a way to provide a value for that parameter when the tool flow is run?

@mithro @acomodi @tmichalak @mkurc-ant Would be interested in any feedback you can provide.

Please specify the tool. For:

  • Yosys with UHDM plugin: -Pparameter=value overrides a toplevel module parameter
    • using Surelog separately: add it to the command, i.e. surelog -parse -Pparameter=value top.sv, then use read_uhdm in Yosys
    • using UHDM frontend directly (which uses Surelog under the hood): add it to the read_verilog_with_uhdm command, i.e. read_verilog_with_uhdm -parse -Pparameter=value top.sv
  • Yosys Verilog frontend: this issue suggests to use chparam in Yosys script

Please let me know if you have any further questions.

@rkapuscik Thanks for the info - very helpful!