rkapuscik

Pinned Repositories

• f4pga-examples

  Example designs showing different ways to use F4PGA toolchains.

  Language:Verilog2712416679

• Surelog

  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

  Language:C++3782792068

• sv-tests

  Test suite designed to check compliance with the SystemVerilog standard.

  Language:SystemVerilog3051928075

• synlig

  SystemVerilog synthesis tool

  Language:Verilog1771625023

• UHDM

  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

  Language:C++2041911540

• verible

  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

  Language:C++1.4k49968217

• flatbuffers

  FlatBuffers: Memory Efficient Serialization Library

  Language:C++23.6k6442.4k3.3k

• valentyusb

  FPGA USB stack written in LiteX

  Language:Python126151026

• opentitan

  OpenTitan: Open source silicon root of trust

  Language:SystemVerilog2.6k1076.9k794

• verilator

  Verilator open-source SystemVerilog simulator and lint system

  Language:C++2.6k733.6k628

rkapuscik's Repositories