chipsalliance/f4pga-examples

Array does not work with integers

Closed this issue · 6 comments

When declaring an array, only the rightmost value will be read correctly while the rest will be read as 0. The SV is accepted and implemented and a bit-stream is generated. Only then can you see that the values are incorrect. In the following example, indices 0-6 will be read as 0 while index 7 will be read as 3.
ex:
logic[1:0] modmem[8] = '{0, 1, 2, 3, 0, 1, 2, 3};

This can be avoided if the width of each value is specified (in hex, decimal, or binary). In the next example, all values will be read correctly when referenced.
ex:
logic[1:0] modmem[8] = '{2'00, 2'b01, 2'b10, 2'b11, 2'd0, 2'd1, 2'h2, 2'h3};

When a mix of integers and specified widths are used, the rightmost integer will cause everything to the left of it to become 0. In the example, indices 0-4 will be read as 0 while indices 5-7 will be read correctly.
ex:
logic[1:0] modmem[8] = '{0, 1, 2'b10, 2'b11, 2'd00, 1, 2'b10, 2'h3};

Note:

This issue uses the same code that nelsobe found to be a problem in Yosys in issue #263 .
This issue is for Surelog, which parses it and results in a faulty bitsream.

Example: integer_in_array.zip

Thanks for reporting, we'll look into it.

This should be already fixed, please update the plugin to the newest version as described here to verify.

We have re-tested this with the latest plugin and the design works now. However, we want fixes to be available to all users when they use the main install. I re-installed the tool-chain with the latest install instructions and this is not fixed without manually updating the plugin.

FYI - @kgugala

Retested and it works