/cpu

CPU - Verilog + Rust

Primary LanguageCMake

CPU - Verilog + Rust

Inspired by yupferris xenowing project, this is a crazy hydra project of rust, c++, and verilog driven by Cargo and cmake.

Most of the cmake heavy lifting comes from the logic project, although I modifed the verilator support to use cmake instead of make to compile.

The test_bench crate is based upon looking at verilator blog by ZipCPU.