Changes for bump BOOM in template branch and last rocket-chip master

[VaginAY]

ucb-bar/riscv-boom@9d34962ed9fbab33df630fae643058301bd944b9
chipsalliance/rocket-chip@61ef560

Diff list for boom:

diff --git a/src/main/scala/common/parameters.scala b/src/main/scala/common/parameters.scala
index f510be5..d3305bb 100644
--- a/src/main/scala/common/parameters.scala
+++ b/src/main/scala/common/parameters.scala
@@ -39,6 +39,7 @@ case class BoomCoreParams(
    enableBpdUSModeHistory: Boolean = false,
    enableBpdF2Redirect: Boolean = false,
    enableBpdF3Redirect: Boolean = true,
+   useAtomicsOnlyForIO: Boolean = false,
    btb: BTBsaParameters = BTBsaParameters(),
    tage: Option[TageParameters] = None,
    gshare: Option[GShareParameters] = None,
diff --git a/src/main/scala/exu/core.scala b/src/main/scala/exu/core.scala
index 0fa6099..32bd505 100755
--- a/src/main/scala/exu/core.scala
+++ b/src/main/scala/exu/core.scala
@@ -275,7 +275,7 @@ class BoomCore(implicit p: Parameters, edge: freechips.rocketchip.tilelink.TLEdg
    if (fetchWidth == 1)
    {
       fetch_unit.io.imem.resp.bits.mask := UInt(1)
-      fetch_unit.io.imem.resp.bits.btb.bits.bridx := UInt(0)
+      fetch_unit.io.imem.resp.bits.btb.bridx := UInt(0)
    }
    fetch_unit.io.br_unit <> br_unit
    fetch_unit.io.tsc_reg           := debug_tsc_reg
diff --git a/src/main/scala/ifu/ScratchpadSlavePort.scala b/src/main/scala/ifu/ScratchpadSlavePort.scala
index fa1dd29..76339a9 100644
--- a/src/main/scala/ifu/ScratchpadSlavePort.scala
+++ b/src/main/scala/ifu/ScratchpadSlavePort.scala
@@ -123,7 +123,7 @@ trait CanHaveBoomScratchpad extends HasHellaCache with HasBoomICacheFrontend {
       val xbar = LazyModule(new TLXbar)
       xbar.node := slaveNode
       xbarPorts.foreach { case (port, bytes) =>
-        (Seq(port, TLFragmenter(bytes, cacheBlockBytes, earlyAck=true))
+        (Seq(port, TLFragmenter(bytes, cacheBlockBytes, earlyAck=EarlyAck.PutFulls))
           ++ (xBytes != bytes).option(TLWidthWidget(xBytes)))
           .foldRight(xbar.node:TLOutwardNode)(_ := _)
       }
diff --git a/src/main/scala/ifu/fetch.scala b/src/main/scala/ifu/fetch.scala
index 156b1db..6e751a3 100644
--- a/src/main/scala/ifu/fetch.scala
+++ b/src/main/scala/ifu/fetch.scala
@@ -493,8 +493,6 @@ class FetchUnit(fetch_width: Int)(implicit p: Parameters) extends BoomModule()(p
    // **** Assertions ****
    //-------------------------------------------------------------
 
-   assert (!(io.imem.resp.bits.btb.valid), "[bpd_pipeline] BTB predicted, but it's been disabled.")
-
    // check if enqueue'd PC is a target of the previous valid enqueue'd PC.
 
    // clear checking if misprediction/flush/etc.
@@ -625,11 +623,10 @@ class FetchUnit(fetch_width: Int)(implicit p: Parameters) extends BoomModule()(p
             )
       }
 
-      printf("----BrPred2:(%c,%c,%d) [btbtarg: 0x%x]\n"
-         , Mux(io.imem.resp.bits.btb.valid, Str("H"), Str("-"))
-         , Mux(io.imem.resp.bits.btb.bits.taken, Str("T"), Str("-"))
-         , io.imem.resp.bits.btb.bits.bridx
-         , io.imem.resp.bits.btb.bits.target(19,0)
+      printf("----BrPred2:(%c,%d) [btbtarg: 0x%x]\n"
+         , Mux(io.imem.resp.bits.btb.taken, Str("T"), Str("-"))
+         , io.imem.resp.bits.btb.bridx
+         , io.imem.resp.bits.btb.target(19,0)
          )
 
       // Fetch Stage 3

[ccelio]

Thanks for the diff! Very helpful.