gnleaf

gnleaf's Stars

• ocornut/imgui

  Dear ImGui: Bloat-free Graphical User interface for C++ with minimal dependencies

  Language:C++59.4k1k5.9k10.1k

• google/leveldb

  LevelDB is a fast key-value storage library written at Google that provides an ordered mapping from string keys to string values.

  Language:C++36.2k1.3k7567.8k

• chromium/chromium

  The official GitHub mirror of the Chromium source

  Language:C++18.7k56306.9k

• abseil/abseil-cpp

  Abseil Common Libraries (C++)

  Language:C++14.7k5908712.6k

• Z3Prover/z3

  The Z3 Theorem Prover

  Language:C++10.2k1795.5k1.5k

• odin-lang/Odin

  Odin Programming Language

  Language:Odin6.6k831.9k572

• LeiWang1999/FPGA

  帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

  3.8k624656

• wavedrom/wavedrom

  :ocean: Digital timing diagram rendering engine

  Language:JavaScript2.9k90339361

• steveicarus/iverilog

  Icarus Verilog

  Language:C++2.8k135710520

• ghdl/ghdl

  VHDL 2008/93/87 simulator

  Language:VHDL2.3k1002.2k358

• verilog-to-routing/vtr-verilog-to-routing

  Verilog to Routing -- Open Source CAD Flow for FPGA Research

  Language:C++1k68998386

• YosysHQ/oss-cad-suite-build

  Multi-platform nightly builds of open source digital design and verification tools

  Language:Shell784288971

• KarypisLab/METIS

  METIS - Serial Graph Partitioning and Fill-reducing Matrix Ordering

  Language:C6681470136

• nturley/netlistsvg

  draws an SVG schematic from a JSON netlist

  Language:JavaScript619269678

• MikePopoloski/slang

  SystemVerilog compiler and language services

  Language:C++58229664130

• kahypar/kahypar

  KaHyPar (Karlsruhe Hypergraph Partitioning) is a multilevel hypergraph partitioning framework providing direct k-way and recursive bisection based partitioning algorithms that compute solutions of very high quality.

  Language:C++4201912791

• YosysHQ/arachne-pnr

  Place and route tool for FPGAs

  Language:C++413637172

• KaHIP/KaHIP

  KaHIP -- Karlsruhe HIGH Quality Partitioning.

  Language:C++384227795

• vczh/GacUIBlog

  记录 GacUI 开发10年来背后的故事，以及对架构设计的考量。

  Language:C++3702227

• chipsalliance/Surelog

  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

  Language:C++3532691567

• Xilinx/RapidWright

  Build Customized FPGA Implementations for Vivado

  Language:Java28627247108

• lsils/mockturtle

  C++ logic network library

  Language:C++2041971136

• xupsh/Digital-Design-Lab

  Language:VHDL20193120

• lsils/lstools-showcase

  Showcase examples for EPFL logic synthesis libraries

  Language:CSS17615031

• KarypisLab/ParMETIS

  ParMETIS - Parallel Graph Partitioning and Fill-reducing Matrix Ordering

  Language:C10651742

• intel/fpga-partial-reconfig

  Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow

  Language:SystemVerilog8627340

• nbulsi/also

  A logic synthesis tool

  Language:C++635430

• torc-isi/torc

  Torc: Tools for Open Reconfigurable Computing

  Language:C++3912225

• nianzelee/threABC

  Threshold logic operation within ABC

  Language:C7204

• zfchu/mockturtle

  C++ logic network library

  Language:C++1103