google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0

Issues

• Gate level verilog modules are horribly broken and unusable

  #24 opened 2 years ago by RTimothyEdwards
  16

• gf180mcu_fd_sc_mcu7t5v0_mux2_1 is seemingly not DRC clean

  #23 opened a year ago by gatecat
  8

• Technology LEF files have incorrect CPERSQDIST

  #30 opened 2 years ago by RTimothyEdwards
  15

• liberty issues with yosys

  #28 opened 2 years ago by kareefardi
  0

• Set up readthedocs pull request rendering

  #13 opened 2 years ago by mithro
  1

• Get the foss-eda-tools.googlesource.com mirror happening

  #1 opened 2 years ago by mithro
  1

• .spice netlist is messed up due to label placement

  #25 opened 2 years ago by andylithia
  1

• Missing Resistance for vias in tech lef

  #19 opened 2 years ago by kareefardi
  14

• Missing SITE definition

  #18 opened 2 years ago by kareefardi
  3

• Miss-match in metal layer names between cells lef and tech lef

  #16 opened 2 years ago by kareefardi
  0

• Figure out what is going on with the fill schematic rendering

  #12 opened 2 years ago by mithro
  0

• Figure out how to fix the flip flop schematic rendering

  #11 opened 2 years ago by mithro
  0

• Figure out how to fix the buffers schematic rendering

  #10 opened 2 years ago by mithro
  0

• Add missing definition.json files for each standard cell

  #3 opened 2 years ago by mithro
  0

• Add verilog test benches for each of the standard cells.

  #4 opened 2 years ago by mithro
  0

• CI should check that the standard cells pass the GF180MCU DRC rules

  #2 opened 2 years ago by mithro
  0