grigoriy-chirkov

grigoriy-chirkov's Stars

• torvalds/linux

  Linux kernel source tree

  Language:C178k7.9k053.1k

• CompVis/stable-diffusion

  A latent text-to-image diffusion model

  Language:Jupyter Notebook67.4k56070910.1k

• nextcloud/server

  ☁️ Nextcloud server, a safe home for all your data

  Language:PHP26.6k55118.7k4k

• fastai/fastbook

  The fastai book, published as Jupyter Notebooks

  Language:Jupyter Notebook21.5k5072358.3k

• tonybeltramelli/pix2code

  pix2code: Generating Code from a Graphical User Interface Screenshot

  Language:Python11.9k1.2k01.4k

• Zelda64Recomp/Zelda64Recomp

  Static recompilation of Majora's Mask (and soon Ocarina of Time) for PC (Windows/Linux)

  Language:C5.2k97343257

• google/skywater-pdk

  Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

  Language:Python2.9k152270382

• openhwgroup/cva6

  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

  Language:Assembly2.2k911k670

• telegram-sms/telegram-sms

  An SMS-forwarding Robot Running on Your Android Device.

  Language:Java1.7k2913161

• aws/aws-fpga

  Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

  Language:VHDL1.5k232167513

• The-OpenROAD-Project/OpenROAD

  OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

  Language:Verilog1.5k521.3k525

• The-OpenROAD-Project/OpenLane

  OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

  Language:Python1.3k59946370

• rsd-devel/rsd

  RSD: RISC-V Out-of-Order Superscalar Processor

  Language:SystemVerilog956344297

• PrincetonUniversity/openpiton

  The OpenPiton Platform

  Language:Assembly6255767212

• karlrupp/microprocessor-trend-data

  Data repository for my blog series on microprocessor trend data.

  Language:Gnuplot49449978

• ZipCPU/wb2axip

  Bus bridges and other odds and ends

  Language:Verilog467315296

• sld-columbia/esp

  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

  Language:C32626117105

• UIUC-ChenLab/scalehls

  A scalable High-Level Synthesis framework on MLIR

  Language:MLIR215156145

• os-fpga/1st-CLaaS

  Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications

  Language:C196161942

• HewlettPackard/mcpat

  An integrated power, area, and timing modeling framework for multicore and manycore architectures

  Language:C++15810565

• PrincetonUniversity/faas-profiler

  An open source tool for testing and profiling FaaS and serverless platforms

  Language:Python10691229

• PrincetonUniversity/accelerator-wall

  Repository for the tools and non-commercial data used for the "Accelerator wall" paper.

  Language:Python478112

• stevehuanghe/image_captioning

  Image captioning models in PyTorch

  Language:Jupyter Notebook3711010

• PrincetonUniversity/smappic

  Language:Assembly19301

• vegaluisjose/aws-fpga-notes

  Amazon F1 instance walk through tutorial

  7201