Pinned Repositories
elf2mif
Utility to convert an ELF file into a Memory Initialization File (MIF)
binutils-gdb
A mirror of the upstream binutils-gdb repository for ARC specific work
adventofcode
My solutions to Advent of Code (https://adventofcode.com/)
corev-binutils-gdb
cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
cv32e40s
4 stage, in-order, secure RISC-V core based on the CV32E40P
cv32e40x
4 stage, in-order, compute RISC-V core based on the CV32E40P
cv32e41p
4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
programs
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
riscv-dbg
RISC-V Debug Support for our PULP RISC-V Cores
jm4rtin's Repositories
jm4rtin/adventofcode
My solutions to Advent of Code (https://adventofcode.com/)