jm4rtin

EM Microelectronic-US Inc.Colorado Springs, CO, USA

Pinned Repositories

elf2mif
Utility to convert an ELF file into a Memory Initialization File (MIF)
Language:C++00
binutils-gdb
A mirror of the upstream binutils-gdb repository for ARC specific work
Language:C13 34 3510
adventofcode
My solutions to Advent of Code (https://adventofcode.com/)
Language:Python00
corev-binutils-gdb
Language:C9 17 4026
cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Language:SystemVerilog899 83 470397
cv32e40s
4 stage, in-order, secure RISC-V core based on the CV32E40P
Language:SystemVerilog125 19 9022
cv32e40x
4 stage, in-order, compute RISC-V core based on the CV32E40P
Language:SystemVerilog195 16 20949
cv32e41p
4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
Language:SystemVerilog26 15 1211
programs
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
Language:HTML181 34 10097
riscv-dbg
RISC-V Debug Support for our PULP RISC-V Cores
Language:SystemVerilog196 20 7070

jm4rtin/adventofcode
My solutions to Advent of Code (https://adventofcode.com/)
Language:Python00