Pinned Repositories
fastvdma
Antmicro's fast, vendor-neutral DMA IP in Chisel
topwrap
A Python package for generating HDL wrappers and top modules for HDL sources
Cores-VeeR-EL2
VeeR EL2 Core
cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
xls
XLS: Accelerated HW Synthesis
bazel_rules_hdl
Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)
gha-playground
pyuvm
The UVM written in Python
OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
verilator
Verilator open-source SystemVerilog simulator and lint system
mczyz-antmicro's Repositories
mczyz-antmicro/gha-playground
mczyz-antmicro/pyuvm
The UVM written in Python