Micro Electronics Research Laboratory
A non-profit organization fostering research on IoT, AI, and ML-based architectures leveraging the open-source RISC-V ISA.
Pakistan
Pinned Repositories
azadi-soc
Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.
buraq_mini
This repository contains the 5 stage pipelined CPU implemented on the RISC-V ISA and Chisel hardware construction language (HDL)
caravan
A caravan equipped with API for creating bus protocols in Chisel with ease.
Google-Summer-of-Code
Project ideas list for Google Summer of Code.
Ibtida
A basic System on a Chip (SoC) based on the Buraq core for the Internet of Things (IoT).
nucleusrv
NucleusRV - A 32-bit 5 staged pipelined risc-v core.
OpenTCAM
An open-source Ternary Content Addressable Memory (TCAM) compiler.
SIngle-Cycle-RISC-V-In-Verilog
This repository contains the verilog code files of Single Cycle RISC-V architecture
TileLink
TileLink Uncached Lightweight (TL-UL) implementation on Chisel.
vaquita
Micro Electronics Research Laboratory 's Repositories
merledu/Riscv-Single-Cycle-Cores
This repository contains the implementation of RISC-V Single Cycle Cores done by Undergraduate Students by using CHISEL and Functional Programming w/ Scala
merledu/Scala-Chisel-Learning-Journey
This repository is for students to go through the Learning Journey for CHISEL and Funcitonal Programming with SCALA also perform tasks related to it.
merledu/common_peripheral_vips
merledu/azadi-verify
This repository contains tests (in C and assembly both), benchmarks and the test-benches for the verification of Azadi SoC.
merledu/Buraq-compressed-assembler
This is the compressed assembler for RISC-V.
merledu/common_peripheral_ips
This repository contains generic peripheral IPs. These IPs can be used as memory mapped device with various bus interfaces like, Tilelink, AXI, AXI-Lite and APB.
merledu/jigsaw
A platform containing useful peripherals implemented in Chisel that can be attached together to complete the puzzle (SoC).
merledu/Rev-Soc
merledu/verification_training
verification training
merledu/azadi-sdk
Software Developement Kit (SDK) for Azadi-SoC
merledu/caravel_azadi_soc_iii_dft
This project is the extended version of Azadi-SoC, which includes all of the peripherals which were in Azadi-II and few more this time, which were not stable at the time of Azadi-II. The Azadi-III includes the following peripherals. PWM 2-Channel, OpenRAM 1KB x 4 for ICCM 1KB x 4 for DCCM Ibex core(named as brq_core) FPU (single-precision) TileLink (UL) UART QSPI SPI GPIOs Design Goals: Azadi-III is aimed to extend the base ibex core(RV32IMC) with a fully functional single precision floating point unit and RISCV compliant debug module for on chip debugging and some standard peripherals for communicating with other devices. all these modules will be interlinked using standard Tilelink Bus protocol. The project aims at adding DFT support to Caravel chip to enable post fabrication testing using Automatic Testing Equipment (ATE). Scan chain is applied to making a design testable , observable and controllable after it has been manufactured.
merledu/caravel_soc_now
merledu/fpnew
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
merledu/nucleusrv-1
NucleusRV - A 32-bit 5 staged pipelined risc-v core.
merledu/porting-docs
This repo contains multiple documentations related to linux porting on RISC-V. Also, running TFLite Models with Zephyr RTOS on RENODE upon RISC-V.
merledu/Quad_SPI
Quad SPI interface for the micron flash available on arty a7-35t FPGA board
merledu/SoC-Now-Generator
An open source Mini SoC Generator which will generate SoC based on parameters.
merledu/Caravel_N_M_P
merledu/Azadi_II_sky130
merledu/AZADI_TSMC65_TAPEOUT
The repository would contain the data like RTL, Documentation, Verification, and APR pertaining to the paid tape out
merledu/caravel_NMP
https://caravel-user-project.readthedocs.io
merledu/circt
Circuit IR Compilers and Tools
merledu/Ghazi_DFT
merledu/Matrixize
A systolic array based Generic Matrix Multiply (GeMM) Accelerator with generic interface
merledu/mdu_rv32
Multiplication and Division Unit for RISCV32 Core In CHISEL
merledu/MERL-Softwares
merledu/pyfive-mpw1-postmortem
To bringup Ibtida and Ghazi SoC
merledu/Rev-Soc-ASIC
merledu/Rev-SoC-FPGA
FPGA model of SweRV-EL2 based System on chip
merledu/riscv-dv
Random instruction generator for RISC-V processor verification