Micro Electronics Research Laboratory

A non-profit organization fostering research on IoT, AI, and ML-based architectures leveraging the open-source RISC-V ISA.

Pakistan

Pinned Repositories

azadi-soc
Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.
Language:SystemVerilog27 4 89
buraq_mini
This repository contains the 5 stage pipelined CPU implemented on the RISC-V ISA and Chisel hardware construction language (HDL)
Language:Scala8 1 196
caravan
A caravan equipped with API for creating bus protocols in Chisel with ease.
Language:Scala14 2 1111
Google-Summer-of-Code
Project ideas list for Google Summer of Code.
11 1 02
Ibtida
A basic System on a Chip (SoC) based on the Buraq core for the Internet of Things (IoT).
Language:Verilog4 1 02
nucleusrv
NucleusRV - A 32-bit 5 staged pipelined risc-v core.
Language:C61 3 2324
OpenTCAM
An open-source Ternary Content Addressable Memory (TCAM) compiler.
Language:Python22 2 112
SIngle-Cycle-RISC-V-In-Verilog
This repository contains the verilog code files of Single Cycle RISC-V architecture
Language:Verilog20 2 16
TileLink
TileLink Uncached Lightweight (TL-UL) implementation on Chisel.
Language:Scala20 4 1510
vaquita
Language:FIRRTL13 1 16

Micro Electronics Research Laboratory 's Repositories

merledu/symbiflow-magic
This repository contains a makefile to easily install Symbiflow for the Xilinx 7 Series boards.
Language:Makefile10 1 12
merledu/azadi
[Deprecated] Azadi is an SoC with 32 bit RISC-V CPU core.
Language:SystemVerilog8 2 69
merledu/buraq_mini
This repository contains the 5 stage pipelined CPU implemented on the RISC-V ISA and Chisel hardware construction language (HDL)
Language:Scala8 1 196
merledu/OpenLane_Workshop
This repository contains the training material for Tapeout Pakistan OpenLane workshop conducted by MERL-UIT.
Language:Verilog8 0 09
merledu/picofoxy
Pipelined In-order Core for Artix-7 Arty-35T board
Language:Scala75
merledu/jigsaw
A platform containing useful peripherals implemented in Chisel that can be attached together to complete the puzzle (SoC).
Language:Scala3 1 27
merledu/Self-Checking-Tests
Language:C3 1 03
merledu/caravel_azadi_soc
https://caravel-user-project.readthedocs.io
Language:Verilog21
merledu/mdu
M-extension for RISC-V cores.
Language:Verilog2 0 01
merledu/nova
An opensource ariane based SoC on aws-fpga
Language:VHDL2 0 01
merledu/Tapeout_Pakistan_Training
2 0 03
merledu/Tcam
This repository contains SRAm based TCAM (ternary content addrerssable memory) IP.
2
merledu/azadi_apr
This repo hold all of the source files and apr file for Azadi SoC.
Language:Verilog12
merledu/briscv-merl
This repo holds the BRISC-V cores, used for the MERL APR training.
Language:Verilog1 0 02
merledu/BURQ-IDE
This Repository Contains Source Code for the Burq-ide project
Language:Python13
merledu/fpu_div_sqrt_mvp
[UNRELEASED] FP div/sqrt unit for transprecision
Language:SystemVerilog1
merledu/ideas-2022
Ideas for the future
11
merledu/ML-AI-Learning-Journey
In this repository there are multiple projects related to Artificial Intelligence.
Language:Python1 0 02
merledu/porting-docs
This repo contains multiple documentations related to linux porting on RISC-V. Also, running TFLite Models with Zephyr RTOS on RENODE upon RISC-V.
1 0 12
merledu/Porting-Progress
11
merledu/rv_fpu_wrapper
A wrapper use to connect open-source FPU with RISC-V CPU.
1 0 01
merledu/ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.9, working as a coprocessor to CORE-V's CVA6 core
merledu/Azadi_II_sky130
Language:Verilog0 1
merledu/BAG_framework
merledu/caravel_azadi_soc_iii
Language:Verilog
merledu/Cores-SweRV-EH2
merledu/Cores-SweRVolf
FuseSoC-based SoC for SweRV EH1
merledu/Documents
This repo contains all the documents regarding MERL activities
merledu/open_mpw_precheck
1
merledu/timer
Chisel implementation of timer which has generic interface and we can connect it with any SoC using jigsaw framework.