Micro Electronics Research Laboratory
A non-profit organization fostering research on IoT, AI, and ML-based architectures leveraging the open-source RISC-V ISA.
Pakistan
Pinned Repositories
azadi-soc
Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.
buraq_mini
This repository contains the 5 stage pipelined CPU implemented on the RISC-V ISA and Chisel hardware construction language (HDL)
caravan
A caravan equipped with API for creating bus protocols in Chisel with ease.
Google-Summer-of-Code
Project ideas list for Google Summer of Code.
Ibtida
A basic System on a Chip (SoC) based on the Buraq core for the Internet of Things (IoT).
nucleusrv
NucleusRV - A 32-bit 5 staged pipelined risc-v core.
OpenTCAM
An open-source Ternary Content Addressable Memory (TCAM) compiler.
SIngle-Cycle-RISC-V-In-Verilog
This repository contains the verilog code files of Single Cycle RISC-V architecture
TileLink
TileLink Uncached Lightweight (TL-UL) implementation on Chisel.
vaquita
Micro Electronics Research Laboratory 's Repositories
merledu/SIngle-Cycle-RISC-V-In-Verilog
This repository contains the verilog code files of Single Cycle RISC-V architecture
merledu/RISC-V-single-cycle-core-Logisim
This repository is for RISC-V single cycle core
merledu/5-Stage-Pipeline-RISC-V-Architecture-in-Verilog
This repository contains the verilog cde files of 5 stage Pipeline RISC-V architecture
merledu/OpenFabric
Open source generator for creating customisable bus topologies (Point-to-point, Shared Bus, CrossBar Switch) based on the bus protocol type provided by the user (AHB, Wishbone, TileLink)
merledu/Shaheen-Core
This core is based on a SIngle Cycle RISC-V implementation. It is the part of the Project Azm-e-Nau initiated by MERL-UIT.
merledu/Ababeel-Core
This core is based on a SIngle Cycle RISC-V implementation. It is the part of the Project Azm-e-Nau initiated by MERL-UIT.
merledu/Burq-Core
This core is based on a SIngle Cycle RISC-V implementation. It is the part of the Project Azm-e-Nau initiated by MERL-UIT.
merledu/Ghaznavi-Core
This core is based on a SIngle Cycle RISC-V implementation. It is the part of the Project Azm-e-Nau initiated by MERL-UIT.
merledu/Ghouri-Core
This core is based on a SIngle Cycle RISC-V implementation. It is the part of the Project Azm-e-Nau initiated by MERL-UIT.
merledu/Markhor-Core
This core is based on a SIngle Cycle RISC-V implementation. It is the part of the Project Azm-e-Nau initiated by MERL-UIT.
merledu/Miraaj-Core
This core is based on a SIngle Cycle RISC-V implementation. It is the part of the Project Azm-e-Nau initiated by MERL-UIT.
merledu/Parwaz-Core
This core is based on a SIngle Cycle RISC-V implementation. It is the part of the Project Azm-e-Nau initiated by MERL-UIT.
merledu/RISC-V-Single-Cycle-Core-Chisel
merledu/RISC-V-Single-Cycle-Logisim
This repository contains the implementation of the RISC-V Single Cycle Core on Logisim
merledu/Zarb-Core
This core is based on a SIngle Cycle RISC-V implementation. It is the part of the Project Azm-e-Nau initiated by MERL-UIT.
merledu/Zarrar-Core
This core is based on a SIngle Cycle RISC-V implementation. It is the part of the Project Azm-e-Nau initiated by MERL-UIT.
merledu/Zulfiqar-Core
This core is based on a SIngle Cycle RISC-V implementation. It is the part of the Project Azm-e-Nau initiated by MERL-UIT.