necaticakaci

necaticakaci's Stars

• eclipse-theia/theia

  Eclipse Theia is a cloud & desktop IDE framework implemented in TypeScript.

  Language:TypeScript19.9k2967.1k2.5k

• MarlinFirmware/Marlin

  Marlin is an optimized firmware for RepRap 3D printers based on the Arduino platform. Many commercial 3D printers come with Marlin installed. Check with your vendor if you need source code for your specific machine.

  Language:C++16.2k89714.8k19.2k

• mit-pdos/xv6-riscv

  Xv6 for RISC-V

  Language:C7k95962.6k

• enjoy-digital/litex

  Build your hardware, easily!

  Language:C2.9k97814557

• BrunoLevy/learn-fpga

  Learning FPGA, yosys, nextpnr, and RISC-V

  Language:C++2.5k8474242

• nvdla/hw

  RTL, Cmodel, and testbench for NVDLA

  Language:Verilog1.7k167347567

• ucb-bar/chipyard

  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

  Language:Scala1.6k86660632

• stnolting/neorv32

  :desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

  Language:VHDL1.6k51196219

• robpike/ivy

  ivy, an APL-like calculator

  Language:Go1.3k5979103

• openhwgroup/cvw

  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

  Language:SystemVerilog24934196177

• sifive/freedom-tools

  Tools for SiFive's Freedom Platform

  Language:Makefile217654452

• eminfedar/fedar-f1-rv64im

  5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.

  Language:Verilog1847317

• omerguzelelectronicguy/CustomRISC-V_LLVM_Backend

  This is a simple tutorial to show LLVM-Backend Steps.

  Language:C++3200