omutlu

Pinned Repositories

• CROW

  Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA 2019 paper "CROW: A Low-Cost Substrate for Improving DRAM Performance, Energy Efficiency, and Reliability". Paper is at: https://people.inf.ethz.ch/omutlu/pub/CROW-DRAM-substrate-for-performance-energy-reliability_isca19.pdf.

  Language:C++156111

• DAMOV

  DAMOV is a benchmark suite and a methodical framework targeting the study of data movement bottlenecks in modern applications. It is intended to study new architectures, such as near-data processing. Described by Oliveira et al. (preliminary version at https://arxiv.org/pdf/2105.03725.pdf)

  Language:C++7242316

• DRAM-Bender

  DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art DDR4 modules of different form factors. Five prototypes are available on different FPGA boards. Described in our preprint: https://arxiv.org/pdf/2211.05838.pdf

  Language:VHDL37755

• MQSim

  MQSim is a fast and accurate simulator modeling the performance of modern multi-queue (MQ) SSDs as well as traditional SATA based SSDs. MQSim faithfully models new high-bandwidth protocol implementations, steady-state SSD conditions, and the full end-to-end latency of requests in modern SSDs. It is described in detail in the FAST 2018 paper by Arash Tavakkol et al., "MQSim: A Framework for Enabling Realistic Studies of Modern Multi-Queue SSD Devices" (https://people.inf.ethz.ch/omutlu/pub/MQSim-SSD-simulation-framework_fast18.pdf)

  Language:C++2532749141

• NOCulator

  NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, hierarchical ring, flattened butterfly) and routers (buffered, bufferless, Adaptive Flow Control, minBD, HiRD).

  Language:C#1911

• PiDRAM

  PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory techniques. Prototype on a RISC-V rocket chip system implemented on an FPGA. Described in our paper: https://arxiv.org/abs/2111.00082

  54627

• ramulator

  A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf

  Language:C++5026298204

• ramulator2

  Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf

  Language:C++146123337

• RowPress

  Source code & scripts for experimental characterization and real-system demonstration of RowPress, a widespread read disturbance phenomenon in DRAM that is different from RowHammer. Described in our ISCA'23 paper by Luo et al. at https://people.inf.ethz.ch/omutlu/pub/RowPress_isca23.pdf

  Language:VHDL28701

• Victima

  Victima is a new software-transparent technique that greatly extends the address translation reach of modern processors by leveraging the underutilized resources of the cache hierarchy, as desribed in the MICRO 2023 paper by Kanellopoulos et al. (https://arxiv.org/pdf/2310.04158/)

  Language:C21608

omutlu's Repositories