/stopwatch

Design a Stopwatch with Verilog HDL

Primary LanguageVerilogMIT LicenseMIT

Stopwatch

Design a stopwatch with Verilog HDL

Stopwatch FSM

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When the Start button is pressed, the stopwatch starts or pauses. Pressing the Soft Reset button resets the display to 00.00.00. Pressing the Hard Reset button first displays 0 on the rightmost segment and then resets the display to 00.00.00.

Stopwatch Block Diagram

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Segment Display Controller FSM

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seg_controller FSM