qianwennn

qianwennn's Stars

• huggingface/transformers

  🤗 Transformers: State-of-the-art Machine Learning for Pytorch, TensorFlow, and JAX.

  Language:Python137k1.1k16.4k27.4k

• f/awesome-chatgpt-prompts

  This repo includes ChatGPT prompt curation to use ChatGPT better.

  Language:HTML115k1.5k015.7k

• pjreddie/darknet

  Convolutional Neural Networks

  Language:C25.9k9122.4k21.3k

• OptimalScale/LMFlow

  An Extensible Toolkit for Finetuning and Inference of Large Foundation Models. Large Models for All.

  Language:Python8.3k72419827

• openai/finetune-transformer-lm

  Code and model for the paper "Improving Language Understanding by Generative Pre-Training"

  Language:Python2.2k7442504

• niklasso/minisat

  A minimalistic and high-performance SAT solver

  Language:C++1k4926396

• xiaop1/Verilog-Practice

  HDLBits website practices & solutions

  Language:Verilog697116178

• PyHDI/Pyverilog

  Python-based Hardware Design Processing Toolkit for Verilog HDL

  Language:Python6494594183

• SymbioticEDA/riscv-formal

  RISC-V Formal Verification Framework

  Language:Verilog589394199

• bespoke-silicon-group/basejump_stl

  BaseJump STL: A Standard Template Library for SystemVerilog

  Language:SystemVerilog5363018699

• NVlabs/verilog-eval

  Verilog evaluation benchmark for large language model

  Language:SystemVerilog1969530

• Doragd/Awesome-Paper-List

  A curated list of repositories in which many NLP/CV/ML papers and related area resources are collected.

  1847031

• stanford-centaur/smt-switch

  A generic C++ API for SMT solving. It provides abstract classes which can be implemented by different SMT solvers.

  Language:C++11995645

• stanford-centaur/pono

  Pono: A flexible and extensible SMT-based model checker

  Language:C++8474630

• jerrylioon/Solutions-to-HDLbits-Verilog-sets

  Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).

  Language:Verilog823028

• aman-goel/avr

  Reads a state transition system and performs property checking

  Language:C++764919

• PrincetonUniversity/AutoSVA

  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.

  Language:Python756125

• PrincetonUniversity/ILAng

  A Modeling and Verification Platform for SoCs using ILAs

  Language:C++75139718

• Gy-Hu/HW-Formal-Paper

  Recent papers related to hardware formal verification.

  60408

• cuhk-eda/REST

  REST, a reinforcement learning framework for constructing rectilinear Steiner Minimum tree (RSMT)

  Language:C54539

• cad-polito-it/I99T

  ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino

  Language:VHDL484017

• dselsam/neurocore-public

  NeuroCore: Guiding CDCL with Unsat-Core Predictions

  Language:Python44738

• santoshsmalagi/Benchmarks

  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.

  Language:Verilog38202

• ispras/hdl-benchmarks

  Collection of digital hardware modules & projects (benchmarks)

  Language:Verilog3615710

• The-OpenROAD-Project-Attic/flute3

  Flute3 is an open-source rectilinear Steiner minimum tree heuristic from Iowa State, with UFRGS improvements

  Language:C++265017

• upscale-project/generic-sqed-demo

  Language:Verilog12313

• makaimann/ride-core-demo

  A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core

  Language:Verilog10310

• jrmoserbaltimore/risc-v-cpu-asynchronous

  A RISC-V CPU implementation

  Language:VHDL9411

• Bo-Yuan-Huang/ILAng

  A Modeling and Verification Platform for SoCs using ILAs

  Language:C++3100