rehannasar2002

7-Segment-Display

AI-ChatBot

AI Chatbot application leveraging the MERN Stack and OpenAI, inspired by ChatGPT

ImageProcessing-Verilog

This project revolves around deploying basic Image Processing methods on Vivado and simulating it.

Modern-UI-UX-Banking-App

Modern UI/UX website using React.js & Tailwind CSS

Note-Making-App

Code for the note storing flask web app using Python

Piano-Stairs

Creating a portable musical piano stairs layout using ATMega2560 as the microcontroller

Power_Forecast

Deep Learning Methods for optimizing the integration of solar energy into the power grid

PWM-Shift-Register

To design and implement an 8-bit shift register compatible with PWM Outputs using Verilog HDL

SDA-OpenCV

This project uses OpenCV HOGDescriptor to detect people, calculate their distances from each other, and alert if they are close enough.

Single-bit-Floating-Adder

To design a 32 bit single precision floating point adder/subtractor on the IEEE 754 standard floating point representations.

rehannasar2002/7-Segment-Display

rehannasar2002/AI-ChatBot

AI Chatbot application leveraging the MERN Stack and OpenAI, inspired by ChatGPT

rehannasar2002/ImageProcessing-Verilog

This project revolves around deploying basic Image Processing methods on Vivado and simulating it.

rehannasar2002/Modern-UI-UX-Banking-App

Modern UI/UX website using React.js & Tailwind CSS

rehannasar2002/Note-Making-App

Code for the note storing flask web app using Python

rehannasar2002/Piano-Stairs

Creating a portable musical piano stairs layout using ATMega2560 as the microcontroller

rehannasar2002/Power_Forecast

Deep Learning Methods for optimizing the integration of solar energy into the power grid

rehannasar2002/PWM-Shift-Register

To design and implement an 8-bit shift register compatible with PWM Outputs using Verilog HDL

rehannasar2002/SDA-OpenCV

This project uses OpenCV HOGDescriptor to detect people, calculate their distances from each other, and alert if they are close enough.

rehannasar2002/Single-bit-Floating-Adder

To design a 32 bit single precision floating point adder/subtractor on the IEEE 754 standard floating point representations.

rehannasar2002/sobel

Implementation of Sobel Filter in Verilog

rehannasar2002/Sobel-Edge-Detector