rohinkumar

rohinkumar's Stars

• gradio-app/gradio

  Build and share delightful machine learning apps, all in Python. 🌟 Star to support our work!

  Language:Python34.8k1775.1k2.6k

• Cinnamon/kotaemon

  An open-source RAG-based tool for chatting with your documents.

  Language:Python18.1k1023291.4k

• chipsalliance/rocket-chip

  Rocket Chip Generator

  Language:Scala3.3k1979741.1k

• olofk/fusesoc

  Package manager and build abstraction tool for FPGA/ASIC development

  Language:Python1.2k65393252

• CNugteren/CLBlast

  Tuned OpenCL BLAS

  Language:C++1.1k58331201

• EEVengers/ThunderScope

  ThunderScope GitHub Repo

  Language:ANTLR9504785200

• schoeberl/chisel-book

  Digital Design with Chisel

  Language:TeX7843619144

• SymbioticEDA/riscv-formal

  RISC-V Formal Verification Framework

  Language:Verilog589394199

• jameslzhu/riscv-card

  An unofficial assembly reference for RISC-V.

  Language:TeX462191457

• stevehoover/warp-v

  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

  Language:TL-Verilog23126957

• stanford-mast/nn_dataflow

  Explore the energy-efficient dataflow scheduling for neural networks.

  Language:Python217202282

• StanfordAHA/garnet

  Next generation CGRA generator

  Language:Python1081318012

• capn-freako/PyBERT

  Serial communication link bit error rate tester simulator, written in Python.

  Language:Python1022111455

• matthuszagh/pyems

  High-level python interface to OpenEMS with automatic mesh generation

  Language:Python84145319

• praharshapm/vsdmixedsignalflow

  This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also discusses the steps to modify the current IP layouts inorder to ensure its acceptance by the EDA tools.

  Language:Verilog426315

• SRI-CSL/l3riscv

  An executable specification of the RISCV ISA in L3.

  Language:Ruby4110110

• thoughtworks/hardposit-chisel3

  Chisel library for Unum Type-III Posit Arithmetic

  Language:Scala34647

• dovebutch/tlv-comp

  Language:Java26607

• kmkalpana2001/DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING

  25104

• lesc-ufv/cgra-routing

  SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.

  Language:Verilog11301

• mnnuahg/StamicCGRA

  A static dataflow CGRA with dynamic dataflow execution capability

  Language:Verilog10201

• gary0501/traditional-CGRA

  my ungraduate project, a traditional CGRA with 3x3 PEs

  Language:Verilog8102

• easysoc/easysoc-chisel

  Create new Chisel project based on ProjectWizard and Templates

  Language:Java6212

• dillonhuff/CGRA_verilog_mirror

  Mirror of CGRA verilog generation on kiwi

  Language:Verilog4201

• dillonhuff/CGRA_partial_eval

  Language:Verilog320

• iamharshal/perc

  Posit Enhanced Rocket Chip

  Language:Scala3101

• dillonhuff/ncsim_cgra_test

  Language:Verilog220

• NathanielWroblewski/goflakes

  A local cellular model for snow crystal growth (generating Reiter snowflakes in go-lang)

  Language:Go220

• zachbe/ee272_cgra

  ee272 cgra vectorized PE project

  Language:Verilog2301

• ramonn76/cgra

  Language:Verilog1200