salzhang/Booth-Multiplier

16-bit signed Booth Multiplier

This particular implementation is a high-performance pipelined 16*16bit Booth Multiplier with a 5-stage Wallace tree Structure. It is released subject to the terms of the MIT License which can be found in this distribution of the Verilog code in a file called LICENSE.

Booth Algorithm and Encoding

We can write an n-bit signed binary number in the following format-1:

We can also write it in format-2:

Or format-3:

In format-3, we can successfully "halfen" the number of addtion by applying this truth table:

Wallace Tree

Reference

Reference: https://zhuanlan.zhihu.com/p/127164011