shalan

shalan's Stars

• shalan/SoC-Lab

  Language:Verilog4

• BrunoLevy/TinyPrograms

  Tiny programs from various sources, for testing softcores

  Language:C937

• AUCOHL/RTL-Repo

  RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24

  Language:Python5

• efabless/BusWrap

  Language:Python4

• shalan/IP_Utilities

  AUC Open Hardware Lab (AUCOHL) IP Utilities

  Language:Python26

• efabless/EF_UART

  Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP

  Language:Verilog32

• efabless/ipm

  Open-source IPs Package Manager (IPM)

  Language:Python142

• shalan/ms_i2c

  i2c master controller with an APB interface

  Language:Verilog11

• AUCOHL/vcd-parser

  VCD Parser for Node.js

  Language:JavaScript21

• nhivp/Awesome-Embedded

  A curated list of awesome embedded programming.

  6k924

• shalan/Awesome-Sky130-IPs

  92

• efabless/openlane2

  The next generation of OpenLane, rewritten from scratch with a modular architecture

  Language:Python20638

• AUCOHL/Lighter

  An automatic clock gating utility

  Language:Verilog405

• Prananya123/RTL-Coding

  Language:Verilog224

• Wren6991/Hazard3

  3-stage RV32IMACZb* processor with debug

  Language:Verilog69748

• google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0

  7 track standard cells for GF180MCU provided by GlobalFoundries.

  Language:Verilog228

• christoph-weiser/mpw6

  submission repository for efabless mpw6 shuttle

  Language:Verilog305

• shalan/verilog_coding_guidelines

  41

• Cloud-V/gridfs_stream_local

  Drop-in replacement for GridFS 'chunks' (WIP)

  Language:JavaScript3

• AUCOHL/sky130-builds

  What it says on the tin

  Language:Python41

• shalan/AD_SAR_ADC

  Digital Standard Cells based SAR ADC

  Language:Verilog111

• shalan/SoCBUS

  Set of HDL modules to construct SoC buses

  Language:Verilog41

• donn/yawp

  Yet Another Waveform Parser

  Language:JavaScript3

• tdene/synth_opt_adders

  Prefix tree adder space exploration library

  Language:Python548

• shalan/CSCE4301-WiKi

  CSCE430101 - Embedded Systems Resources

  64

• shalan/Caravel_N5_SoC

  Language:Verilog31

• brabect1/sta_basics_course

  Introductory course into static timing analysis (STA).

  Language:Verilog6318

• AUCOHL/DFFRAM

  Standard Cell Library based Memory Compiler using FF/Latch cells

  Language:Verilog13332

• The-OpenROAD-Project/OpenLane

  OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

  Language:Python1.3k373

• efabless/raptor

  Arm Cortex-M0 based Customizable SoC for IoT Applications

  Language:Assembly129