stineje

stineje's Stars

• Asabeneh/30-Days-Of-Python

  30 days of Python programming challenge is a step-by-step guide to learn the Python programming language in 30 days. This challenge may take more than100 days, follow your own pace. These videos may help too: https://www.youtube.com/channel/UC7PNRuno1rzYPb1xLa4yktw

  Language:Python43.6k8261398.3k

• Dao-AILab/flash-attention

  Fast and memory-efficient exact attention

  Language:Python14.9k1241.2k1.4k

• kokke/tiny-AES-c

  Small portable AES128/192/256 in C

  Language:C4.3k1431641.3k

• riscv-collab/riscv-gnu-toolchain

  GNU toolchain for RISC-V, including GCC

  Language:C3.6k1451.1k1.2k

• dockcross/dockcross

  Cross compiling toolchains in Docker images

  Language:Shell3.3k68311409

• alexforencich/verilog-ethernet

  Verilog Ethernet components for FPGA implementation

  Language:Verilog2.4k119171711

• libtom/libtomcrypt

  LibTomCrypt is a fairly comprehensive, modular and portable cryptographic toolkit that provides developers with a vast array of well known published block ciphers, one-way hash functions, chaining modes, pseudo-random number generators, public key cryptography and a plethora of other routines.

  Language:C1.6k109242464

• chipsalliance/riscv-dv

  Random instruction generator for RISC-V processor verification

  Language:Python1k83351332

• MikePopoloski/slang

  SystemVerilog compiler and language services

  Language:C++64830703142

• RTimothyEdwards/magic

  Magic VLSI Layout Tool

  Language:C50426226107

• riscv-collab/riscv-openocd

  Fork of OpenOCD that has RISC-V support

  Language:C45762398334

• iic-jku/IIC-OSIC-TOOLS

  IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

  Language:Python374136169

• riscv/riscv-crypto

  RISC-V cryptography extensions standardisation work.

  Language:C3713422989

• RTimothyEdwards/open_pdks

  PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open processes.

  Language:Python2982022087

• openhwgroup/cvw

  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

  Language:SystemVerilog28933256200

• CMU-SAFARI/ramulator2

  Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf

  Language:C++265145462

• efabless/caravel_user_project

  https://caravel-user-project.readthedocs.io

  Language:Verilog18630186332

• toddmaustin/bringup-bench

  Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, accelerators, compilers and operating systems. You probably don't need Bringup-Bench, but if you do, you probably need it badly!

  Language:C1516420

• bmurmann/EE628

  EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)

  Language:Jupyter Notebook14415127

• classabbyamp/espresso-logic

  A modern (2017) compilable re-host of the Espresso heuristic logic minimizer.

  Language:C1337138

• riscv-verification/RVVI

  RISC-V Verification Interface

  Language:C80111015

• tdene/synth_opt_adders

  Prefix tree adder space exploration library

  Language:Python558478

• ucb-bar/berkeley-testfloat-3

  TestFloat release 3

  Language:C5340433

• riscv-software-src/riscv-ctg

  Language:Python40192551

• mcjtag/bitonic_sorter

  Bitonic sorter (Batcher's sorting network) written in Verilog.

  Language:Verilog26237

• mattvenn/zero-to-asic-www

  Language:HTML6369

• NickOveracker/StickDiagrammer

  Language:JavaScript6412

• or-tools/cmake_or-tools

  Modern CMake C++ Sample using google/or-tools

  Language:Makefile6310

• jtanx/ImplicationTable

  Generates an implication chart to minimise a finite state machine

  Language:Python220

• Matthew-Otto/Drop-In-JTAG

  Open Source Silicon Development Testing Unit - Senior Design Project

  Language:SystemVerilog1201