logic-synthesis

There are 61 repositories under logic-synthesis topic.

  • awesome-eda

    90

  • lstools-showcase

    Showcase examples for EPFL logic synthesis libraries

    Language:CSS185

  • OpenABC

    OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

    Language:Verilog115
  • DRiLLS

    DRiLLS

    DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)

    Language:Python103

  • LSOracle

    IDEA project source files

    Language:Verilog98

  • cirkit

    A circuit toolkit

    Language:C++96

  • digital-flow

    This is a tutorial on standard digital design flow

    Language:Tcl73

  • also

    A logic synthesis tool

    Language:C++69
  • fiction

    fiction

    An open-source design automation framework for Field-coupled Nanotechnologies

    Language:C++65

  • workcraft

    Toolset to capture, simulate, synthesize and verify graph models

    Language:Java62

  • kitty

    C++ truth table library

    Language:C++51

  • OpenPhySyn

    EDA physical synthesis optimization kit

    Language:Verilog50

  • RDF-2019

    DATC RDF

    Language:Verilog48

  • yosys

    Logic synthesis and ABC based optimization

    Language:C++46

  • lorina

    C++ parsing library for simple formats used in logic synthesis and formal verification

    Language:C++35

  • DRUM

    The Verilog source code for DRUM approximate multiplier.

    Language:Verilog28

  • BLASYS

    An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization

    Language:Verilog27

  • awesome-ml4ls

    Awesome machine learning for logic synthesis

    Language:Python24

  • HOGA

    Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits

    Language:Python22

  • phyLS

    A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Verification""

    Language:C++20

  • BACS

    Benchmarks for Approximate Circuit Synthesis

    Language:Verilog13

  • ABACUS

    ABACUS is a tool for approximate logic synthesis

    Language:C13

  • ACLA

    Software and Hardware models of Approximate Carry-Lookahead Adder with Intelligent Carry Judgement and Correction

    Language:Verilog12

  • VECBEE

    VECBEE: A Versatile Efficiency-Accuracy Configurable Batch Error Estimation Method for Greedy Approximate Logic Synthesis

    Language:C++11

  • easy

    C++ header-only ESOP library

    Language:C++10

  • Awesome-Logic-Synthesis

    A collection of the Logic Synthesis about peoples/papers/projects/tutorials...

    9

  • minecraft-eda

    Electronic design automation for Minecraft

    Language:Python9

  • abc

    Implementing physical synthesis and SDC support into ABC

    Language:C8

  • digital_circuits

    A collection of digital logic circuits

    Language:SystemVerilog7

  • chp2prs

    Automated conversion from CHP to PRS using syntax-directed translation

    Language:C++7

  • nangate

    Yosys passes to syntheize to NaN gates (à la http://tom7.org/nand/)

    Language:C++7

  • FRAIG

    Functionally Reduced And-Inverter Graph

    Language:C++7

  • Advanced_Logic_Synthesis

    Coursework of NTHU CS613200 Advanced Logic Synthesis

    Language:C++5

  • exorcism

    Fast Heuristic Minimization of Exclusive-Sums-of-Products

    Language:C++5

  • ResubALS

    Efficient resubstitution-based approximate logic synthesis

    Language:C++4

  • MECALS

    An approximate logic synthesis tool under the maximum error constraint

    Language:Verilog4