xiaoan109's Stars
massgravel/Microsoft-Activation-Scripts
Open-source Windows and Office activator featuring HWID, Ohook, KMS38, and Online KMS activation methods, along with advanced troubleshooting.
enjoy-digital/litex
Build your hardware, easily!
lowRISC/opentitan
OpenTitan: Open source silicon root of trust
openhwgroup/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
alexforencich/verilog-axi
Verilog AXI components for FPGA implementation
ZipCPU/zipcpu
A small, light weight, RISC CPU soft core
riscv-mcu/e203_hbirdv2
The Ultra-Low Power RISC-V Core
pulp-platform/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
eugene-tarassov/vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
Digilent/vivado-library
pulp-platform/common_cells
Common SystemVerilog components
raysalemi/uvmprimer
Contains the code examples from The UVM Primer Book sorted by chapters.
shinezyy/micro-arch-training
How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design
laforest/FPGADesignElements
A self-contained online book containing a library of FPGA design modules and related coding/design guides.
Nitcloud/Digital-IDE
在vscode上的数字设计开发插件
lizhirui/AXI_spec_chinese
AXI协议规范中文翻译版
OSCPU/ysyx-workbench
kumarrishav14/AXI
VIP for AXI Protocol
Yawei-Ding/ysyx_riscv64_cpu
seonskim/verilog_axi-interconnect
AXI Interconnect
adki/DPI_Tutorial
SystemVerilog Direct Programming Interface (DPI) Tutorial
olofk/wb_intercon
Wishbone interconnect utilities
FPGA-InsideOut/hdlgadgets
human-in-the-loop HDL training tool
hizbi-github/AXI4_Master_Interconnect_Slave
A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple masters arbitration. Simulation waveforms are also included.
Kristoff-starling/ProjectN-CPU
Single Cycle and Pipeline CPU of RISC-V Architecture designed for Digital Design and Computer Organization Experiments 2021, NJU
Ghonimo/Pre_Silicon-AHB-to_APB-Verification
Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
Artityagi123456789/15DaysofUVM
BryanHeBY/NJU_DigitalDesignProject
A RV32I pipeline CPU and applications transplanted from AM, NJU-Project-N
www-asics-ws/wb_conmax
WISHBONE Interconnect
algorithmconquer/ysyx_riscv64_cpu