xiaokamikami

xiaokamikami's Stars

• Anduin2017/HowToCook

  程序员在家做饭方法指南。Programmer's guide about how to cook at home (Simplified Chinese only).

  Language:Dockerfile67.1k4036658.7k

• OpenXiangShan/XiangShan

  Open-source high-performance RISC-V processor

  Language:Scala4.8k87400654

• lokalise/i18n-ally

  🌍 All in one i18n extension for VS Code

  Language:TypeScript4k30777320

• LeiWang1999/FPGA

  帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

  4k644668

• riscv/riscv-isa-manual

  RISC-V Instruction Set Manual

  Language:TeX3.7k206880639

• chipsalliance/rocket-chip

  Rocket Chip Generator

  Language:Scala3.2k1979691.1k

• GPUOpen-Drivers/AMDVLK

  AMD Open Source Driver For Vulkan

  1.7k100341162

• gem5/gem5

  The official repository for the gem5 computer-system architecture simulator.

  Language:C++1.7k723461.2k

• SpinalHDL/SpinalHDL

  Scala based HDL

  Language:Scala1.7k80736329

• phiresky/sqlite-zstd

  Transparent dictionary-based row-level compression for SQLite

  Language:Rust1.4k213249

• cacay/MemoryPool

  An easy to use and efficient memory pool allocator written in C++.

  Language:C++1.2k6510409

• PauperZ/SSRSpeedN

  基于SSRSpeed修改，支持同时进行单线程/多线程测速，并可同时进行流媒体解锁状态测试

  Language:Python1.2k667159

• freechipsproject/chisel-bootcamp

  Generator Bootcamp Material: Learn Chisel the Right Way

  Language:Jupyter Notebook9766877277

• riscv/riscv-v-spec

  Working draft of the proposed RISC-V V vector extension

  Language:Assembly962131704273

• THU-DSP-LAB/ventus-gpgpu

  GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

  Language:Scala618142671

• chipsalliance/chisel-template

  A template project for beginning new Chisel work

  Language:Scala5835135185

• Xilinx/dma_ip_drivers

  Xilinx QDMA IP Drivers

  Language:C57249188421

• xxjwxc/shares

  A-share quantitative system. A股量化系统

  Language:PLpgSQL49694127

• shaojintian/Best_README_template

  🌩最好的中文README模板⚡️Best README template

  24441250

• OpenXiangShan/NEMU

  Language:C23669890

• riscv/riscv-j-extension

  Working Draft of the RISC-V J Extension Specification

  Language:Makefile167336317

• odin2985/FPGA-CNN-accelerator-based-on-systolic-array

  2023集创赛国二，紫光同创杯。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。

  Language:Verilog110219

• cispa/GhostWrite

  Proof-of-concept for the GhostWrite CPU bug.

  Language:C1015116

• OSCPU/ysyxSoC

  Language:Verilog766331

• lshpku/gem5-fs-handbook

  gem5 FS模式实验手册

  Language:Python28105

• mperov/fixSegfaultVCS

  There is segmentation fault of VCS which should be fixed.

  Language:Python28137

• tastynoob/aura-core

  "aura" my super-scalar O3 cpu core

  Language:SystemVerilog24000

• portablejim/BetterBuildersWands

  Language:Java17410921

• shinezyy/gem5_data_proc

  data preprocessing scripts for gem5 output

  Language:Python147012

• kazutoiris/All-You-Need-to-Know-About-QDMA

  All You Need to Know About QDMA

  Language:Tcl3302