Pinned Repositories
AES
🔐 Hardware Implementation Of AES Algorithm in Verilog HDL
CGRAs
Coarse Grained Reconfigurable Arrays with Chisel3
Chatroom
🗣 Chatroom in Rust
ChipyardIntegration
😱 RoCC Accelerator Integration with Chipyard
FIFOMemory
📍 A FIFO Memory Implementation in Verilog HDL
MIPSProcessor
🔮 A 32-bit MIPS Processor Implementation in Verilog HDL
NoCRouter
👶🏻 My first baby steps into the world of NoC
PipelinedARM
💎 A 32-bit ARM Processor Implementation in Verilog HDL
PipelinedMIPS
🔮 A 16-bit MIPS Processor Implementation in Verilog HDL
WMController
✨🐾✨ A Control System for Washing Machine in Verilog HDL
yasnakateb's Repositories
yasnakateb/PipelinedARM
💎 A 32-bit ARM Processor Implementation in Verilog HDL
yasnakateb/CGRAs
Coarse Grained Reconfigurable Arrays with Chisel3
yasnakateb/NoCRouter
👶🏻 My first baby steps into the world of NoC
yasnakateb/MIPSProcessor
🔮 A 32-bit MIPS Processor Implementation in Verilog HDL
yasnakateb/PipelinedMIPS
🔮 A 16-bit MIPS Processor Implementation in Verilog HDL
yasnakateb/WMController
✨🐾✨ A Control System for Washing Machine in Verilog HDL
yasnakateb/AES
🔐 Hardware Implementation Of AES Algorithm in Verilog HDL
yasnakateb/ChipyardIntegration
😱 RoCC Accelerator Integration with Chipyard
yasnakateb/UARTCommunication
☎️ UART Communication Implementation in Verilog HDL
yasnakateb/Blinky
💡A Quartus II project testing the functionality of the Altera Cyclone IV EP4CE6E22C8N board
yasnakateb/ChiselNotes
Chisel3 examples
yasnakateb/Dartris
🏳️ A simple Tetris Game in Dart. Just for fun.
yasnakateb/MSCAllocator
A simple allocator for experimental purposes
yasnakateb/SdramController
🛠 A SDRAM controller in Verilog HDL
yasnakateb/Static-Timing-Analysis-Full-Course
Static Timing Analysis Full Course
yasnakateb/USSalPrediction
💰 Salary prediction
yasnakateb/VectorOps
🏄 Custom IP for vector operations
yasnakateb/aima-python
Python implementation of algorithms from Russell And Norvig's "Artificial Intelligence - A Modern Approach"
yasnakateb/Chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
yasnakateb/Chisel7Segment
BCD to 7 Segment Decoder in Chisel3
yasnakateb/ChiselProcessor
Multicycle processor in Chisel3
yasnakateb/MemoryAllocators
yasnakateb/MNISTNeuralNetwork
✍️ A simple neural network using the MNIST data set to recognize hand-written digits.
yasnakateb/MSAllocator
yasnakateb/OpenCVNotes
OpenCV basics in cpp
yasnakateb/SingleProcessorSystem
💻 A Single Processor System With Gem5
yasnakateb/TensorFlowNotes
TensorFlow for deep learning
yasnakateb/XiangShan
Open-source high-performance RISC-V processor
yasnakateb/yasnakateb
yasnakateb/yasnakateb.github.io
🏠 Personal Website