yesilzeytin

yesilzeytin's Stars

• ggerganov/llama.cpp

  LLM inference in C/C++

  Language:C++74.3k5714.5k10.7k

• adam-maj/tiny-gpu

  A minimal GPU design in Verilog to learn how GPUs work from the ground up

  Language:SystemVerilog8k7325616

• OpenXiangShan/XiangShan

  Open-source high-performance RISC-V processor

  Language:Scala6.2k97506752

• enjoy-digital/litex

  Build your hardware, easily!

  Language:C3.2k96860607

• BrunoLevy/learn-fpga

  Learning FPGA, yosys, nextpnr, and RISC-V

  Language:C++2.7k8776256

• gem5/gem5

  The official repository for the gem5 computer-system architecture simulator.

  Language:C++1.9k714011.4k

• amaranth-lang/amaranth

  A modern hardware definition language and toolchain based on Python

  Language:Python1.7k46825177

• XUANTIE-RV/openc910

  OpenXuantie - OpenC910 Core

  Language:Verilog1.2k4532329

• B-Lang-org/bsc

  Bluespec Compiler (BSC)

  Language:Haskell99147320153

• veryl-lang/veryl

  Veryl: A Modern Hardware Description Language

  Language:Rust5981343733

• ChampSim/ChampSim

  ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture community.

  Language:C++57725231469

• intel/rohd

  The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

  Language:Dart4111428276

• CMU-SAFARI/ramulator2

  Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf

  Language:C++307126467

• svunit/svunit

  Language:SystemVerilog1972015163

• hkust-zhiyao/RTL-Coder

  A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.

  Language:Python17751520

• toddmaustin/bringup-bench

  Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, accelerators, compilers and operating systems. You probably don't need Bringup-Bench, but if you do, you probably need it badly!

  Language:C1516423

• thedatabusdotio/fpga-ml-accelerator

  This repository hosts the code for an FPGA based accelerator for convolutional neural networks

  Language:Verilog1443428

• mayurkubavat/UVM-Examples

  UVM examples and projects

  Language:SystemVerilog12614168

• intel/rohd-hcl

  A hardware component library developed with ROHD.

  Language:Dart9346828

• hpsresearchgroup/scarab

  Joint HPS and ETH Repository to work towards open sourcing Scarab and Ramulator

  Language:C75123840

• wyvernSemi/riscV

  Open source ISS and logic RISC-V 32 bit project

  Language:C++438114

• intel/rohd-vf

  The ROHD Verification Framework is a hardware verification framework built upon ROHD for building testbenches.

  Language:Dart4152314

• mxg/topaz

  Language:SystemVerilog184

• 10x-Engineers/clang-builtin-tutorial

  15201

• AdnanCigtekin/Neon-Riders

  An endless motorcycle game for Mobile using Unity game engine.

  Language:C#9003

• toddmaustin/vip-bench

  VIP-Bench benchmarks for evaluating secure computation frameworks (e.g., HE, MPC, SE, etc...)

  Language:C++9200

• andyongg/yuv2image

  yuv2image is an open source tool for converting YUV format file to image file (i.e. jpg/bmp/png).

  Language:C++7004

• DenizzzGuzell/SPI_VIP

  Verification IP of fully parameterized 4 modes SPI

  Language:SystemVerilog4100

• AhmadHouraniah/FMDSP

  Open-source DSP Block IP Generator

  Language:Verilog20

• AdnanCigtekin/adnancigtekin.github.io

  Language:TypeScript1100