20Mhz

20Mhz's Stars

• vinta/awesome-python

  An opinionated list of awesome Python frameworks, libraries, software and resources.

  Language:Python229k6.1k025k

• github/gitignore

  A collection of useful .gitignore templates

  163k3.4k083.1k

• jlevy/the-art-of-command-line

  Master the command line, in one page

  154k2.8k25414.6k

• ibraheemdev/modern-unix

  A collection of modern/faster/saner alternatives to common unix commands.

  31.3k39481789

• enjoy-digital/litex

  Build your hardware, easily!

  Language:C3.1k97835575

• alexforencich/verilog-ethernet

  Verilog Ethernet components for FPGA implementation

  Language:Verilog2.4k119171709

• chipsalliance/verible

  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

  Language:C++1.4k48963217

• sylefeb/Silice

  Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.

  Language:C++1.3k4520081

• ghostop14/sparrow-wifi

  Next-Gen GUI-based WiFi and Bluetooth Analyzer for Linux

  Language:Python1.3k7288158

• ngscopeclient/scopehal-apps

  ngscopeclient and other client applications for libscopehal.

  Language:C++62930611109

• RTimothyEdwards/magic

  Magic VLSI Layout Tool

  Language:C50426226106

• iic-jku/IIC-OSIC-TOOLS

  IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

  Language:Python372135768

• yne/vcd

  VCD file (Value Change Dump) command line viewer

  Language:C1128912

• westerndigitalcorporation/pyvcd

  Python package for writing Value Change Dump (VCD) files.

  Language:Python109161941

• ben-marshall/verilog-vcd-parser

  A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

  Language:C++906636

• ultraembedded/fat_io_lib

  Small footprint, low dependency, C code implementation of a FAT16 & FAT32 driver.

  Language:C646913

• nickson-jose/vsdstdcelldesign

  This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an openlane flow.

  Language:Verilog637241

• QuickLogic-Corp/quick-feather-dev-board

  100% open source dev kit for EOS S3 MCU+eFPGA SoC supported by fully open source SDK and FPGA Toolchain

  5971014

• tdene/synth_opt_adders

  Prefix tree adder space exploration library

  Language:Python558478

• google/skywater-pdk-sky130-raw-data

  Raw data collected about the SKY130 process technology.

  Language:Jupyter Notebook51141316

• kevinmehall/rust-vcd

  Read and write VCD (Value Change Dump) files in Rust

  Language:Rust416920

• iic-jku/SKY130_SAR-ADC1

  Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license

  Language:Verilog38306

• asinghani/sky130-chip-vis

  Gate-level visualization generator for SKY130-based chip designs.

  Language:Python20502

• carlos-jenkins/csv2vcd

  Signal analyzer CSV to IEEE 1364-2001 VCD file format converter.

  Language:Python114310

• ChrisZonghaoLi/gm_id_gf180mcu

  This repo contains introduction of gm/id method and its application to some OTA design examples.

  Language:Jupyter Notebook9102

• KHermanUBB/SSCS-SoC

  The documentation folder for the project Sonar On Chip being part of the SSCS IEEE Circuits and Systems 2021

  Language:Verilog5106

• IC-UBB/Sonar-on-Chip

  The project is oriented to implement a multichannel signal path for ultrasonic air-coupled sonar based on MEMS wideband digital microphones

  Language:Jupyter Notebook37

• wokwi/wrapped_skullfet

  Skull MOSFET, wrapped for Caravel

  Language:Verilog3211

• diegob94/copperv2

  RISCV Core

  Language:Assembly1103

• Mauricio-xx/RTL_design_workshop

  This repo contain all of my files and documentation of the workshop "RTL design using Verilog with SKY130 Technology"

  1101