ChrisShakkour

ChrisShakkour's Stars

• ashishpatel26/500-AI-Machine-learning-Deep-learning-Computer-vision-NLP-Projects-with-code

  500 AI Machine learning Deep learning Computer vision NLP Projects with code

  21.4k608605.3k

• gjy3035/Awesome-Crowd-Counting

  Awesome Crowd Counting

  2.4k10454480

• basicmi/AI-Chip

  A list of ICs and IPs for AI, Machine Learning and Deep Learning.

  Language:PHP1.7k26725275

• lowRISC/ibex

  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

  Language:SystemVerilog1.4k99843560

• pulp-platform/axi

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  Language:SystemVerilog1.2k39123272

• chipsalliance/riscv-dv

  Random instruction generator for RISC-V processor verification

  Language:Python1k83351333

• openhwgroup/cv32e40p

  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

  Language:SystemVerilog99082485428

• AvrahamRaviv/Deep-Learning-in-Hebrew

  ספר מלא בעברית על למידת מכונה ולמידה עמוקה

  950641495

• syntacore/scr1

  SCR1 is a high-quality open-source RISC-V MCU core in Verilog

  Language:SystemVerilog8855258284

• riscvarchive/riscv-cores-list

  RISC-V Cores, SoC platforms and SoCs

  855584206

• VLSIDA/OpenRAM

  An open-source static random access memory (SRAM) compiler.

  Language:Python85357188206

• riscv/riscv-opcodes

  RISC-V Opcodes

  Language:Python7088570310

• gjy3035/C-3-Framework

  An open-source PyTorch code for crowd counting

  Language:Jupyter Notebook70723112199

• sudhamshu091/32-Verilog-Mini-Projects

  Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

  Language:Verilog60497117

• pulp-platform/common_cells

  Common SystemVerilog components

  Language:SystemVerilog5441959148

• openhwgroup/cvfpu

  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

  Language:SystemVerilog4443764117

• Andarius/piou

  A CLI tool to build beautiful rich text command-line interfaces with type validation.

  Language:Python317745

• pulp-platform/tech_cells_generic

  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)

  Language:SystemVerilog428330

• riscv/riscv-test-env

  Language:C424810108

• wavedrom/schema

  JSON schema for WaveDrom

  Language:JavaScript357010

• amichai-bd/riscv-multi-core-lotr

  RISCV core RV32I/E.4 threads in a ring architecture

  Language:SystemVerilog3061497

• pulp-platform/hwpe-stream

  IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system

  Language:SystemVerilog188119

• vsdip/rvmyth_avsddac_interface

  Language:Verilog14215

• ChrisShakkour/RV32I-MAF-project

  Designinig a Pipeline in-order 5 stage RISC-V core RV32I-MAF

  Language:SystemVerilog81581

• dineshannayya/riscduino_qcore

  Language:Tcl7315

• whyrv/AI-Chip

  A list of ICs and IPs for AI, Machine Learning and Deep Learning.

  Language:Jupyter Notebook10