Eloquencere's Stars
logisim-evolution/logisim-evolution
Digital logic design tool and simulator
alexforencich/verilog-ethernet
Verilog Ethernet components for FPGA implementation
cocotb/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
alexforencich/verilog-axi
Verilog AXI components for FPGA implementation
ultraembedded/riscv
RISC-V CPU Core (RV32IM)
alexforencich/verilog-pcie
Verilog PCI express components
YosysHQ/oss-cad-suite-build
Multi-platform nightly builds of open source digital design and verification tools
Digilent/vivado-library
ben-marshall/awesome-open-hardware-verification
A List of Free and Open Source Hardware Verification Tools and Frameworks
Digilent/vivado-boards
tymonx/logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
veripool/verilog-perl
Verilog parser, preprocessor, and related tools for the Verilog-Perl package
ahmedshahein/DSP-RTL-Lib
RTL Verilog library for various DSP modules
Siddhi-95/AHB-to-APB-Bridge-Verification
Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
Digilent/ZYBO
prajwalgekkouga/AHB-to-APB-Bridge
The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.
bradgrantham/alice5
SPIR-V fragment shader GPU core based on RISC-V
arasgungore/VGA-based-screensaver
A VHDL-based VGA driver to implement a square 41x41 screensaver that cycles through 256 different colors.
Ghonimo/Pre_Silicon-AHB-to_APB-Verification
Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
Digilent/SDSoC-platforms
SDSoC platforms for Digilent Zynq boards
jchengX/MAC_BFM
wifi
nelsoncsc/basic_uvmc_oct
A simple UVM testbench using UVM Connect and Octave
kbbuch/LC3-Verification
Verification of a 5 stage LC3 pipelined CPU with System Verilog and Mentor Graphics ModelSim
srishis/DMA8237A_VERIF
Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench
jg-fossh/IIR_FILTER
IIR Parallel Filter
BhattaraiRajat/Digital-Signal-Processor-Design-in-FPGA
midimaster21b/SHA-Module
A simple SHA-256 implementation in VHDL and Verilog, simulated using a basic UVM testbench.
npatsiatzis/recirculation_mux
nulface/SystemVerilog-VGA-controller
A VGA controller designed in SystemVerilog
quantrpeter/verilog-ethernet
Verilog Ethernet components for FPGA implementation