Eloquencere

Eloquencere's Stars

• logisim-evolution/logisim-evolution

  Digital logic design tool and simulator

  Language:Java4.9k67867636

• alexforencich/verilog-ethernet

  Verilog Ethernet components for FPGA implementation

  Language:Verilog2.3k116168699

• cocotb/cocotb

  cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

  Language:Python1.8k1081.9k511

• alexforencich/verilog-axi

  Verilog AXI components for FPGA implementation

  Language:Verilog1.5k5371447

• ultraembedded/riscv

  RISC-V CPU Core (RV32IM)

  Language:Verilog1.2k5118233

• alexforencich/verilog-pcie

  Verilog PCI express components

  Language:Verilog1.1k5051299

• YosysHQ/oss-cad-suite-build

  Multi-platform nightly builds of open source digital design and verification tools

  Language:Shell837289375

• Digilent/vivado-library

  Language:C5705959312

• ben-marshall/awesome-open-hardware-verification

  A List of Free and Open Source Hardware Verification Tools and Frameworks

  49143546

• Digilent/vivado-boards

  Language:Tcl3964531212

• tymonx/logic

  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

  Language:SystemVerilog26731159

• veripool/verilog-perl

  Verilog parser, preprocessor, and related tools for the Verilog-Perl package

  Language:Perl1201231533

• ahmedshahein/DSP-RTL-Lib

  RTL Verilog library for various DSP modules

  Language:Verilog825130

• Siddhi-95/AHB-to-APB-Bridge-Verification

  Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.

  Language:SystemVerilog681115

• Digilent/ZYBO

  Language:C613311110

• prajwalgekkouga/AHB-to-APB-Bridge

  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.

  Language:Verilog481112

• bradgrantham/alice5

  SPIR-V fragment shader GPU core based on RISC-V

  Language:Verilog3651511

• arasgungore/VGA-based-screensaver

  A VHDL-based VGA driver to implement a square 41x41 screensaver that cycles through 256 different colors.

  Language:VHDL1820

• Ghonimo/Pre_Silicon-AHB-to_APB-Verification

  Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀

  Language:SystemVerilog14103

• Digilent/SDSoC-platforms

  SDSoC platforms for Digilent Zynq boards

  Language:VHDL1212

• jchengX/MAC_BFM

  wifi

  Language:SystemVerilog10102

• nelsoncsc/basic_uvmc_oct

  A simple UVM testbench using UVM Connect and Octave

  Language:SystemVerilog9301

• kbbuch/LC3-Verification

  Verification of a 5 stage LC3 pipelined CPU with System Verilog and Mentor Graphics ModelSim

  Language:SystemVerilog8000

• srishis/DMA8237A_VERIF

  Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench

  Language:SystemVerilog82181

• jg-fossh/IIR_FILTER

  IIR Parallel Filter

  Language:Python5101

• BhattaraiRajat/Digital-Signal-Processor-Design-in-FPGA

  Language:HTML2

• midimaster21b/SHA-Module

  A simple SHA-256 implementation in VHDL and Verilog, simulated using a basic UVM testbench.

  Language:Verilog1290

• npatsiatzis/recirculation_mux

  Language:Python1200

• nulface/SystemVerilog-VGA-controller

  A VGA controller designed in SystemVerilog

  Language:SystemVerilog10

• quantrpeter/verilog-ethernet

  Verilog Ethernet components for FPGA implementation

  Language:Verilog1101