Nado15

Nado15's Stars

• spesmilo/electrum

  Electrum Bitcoin Wallet

  Language:Python7.3k3736.7k3.1k

• riscv/riscv-isa-manual

  RISC-V Instruction Set Manual

  Language:TeX3.5k206847613

• mortbopet/Ripes

  A graphical processor simulator and assembly editor for the RISC-V ISA

  Language:C++2.5k46210270

• BrunoLevy/learn-fpga

  Learning FPGA, yosys, nextpnr, and RISC-V

  Language:C++2.5k8474237

• riscv-software-src/riscv-isa-sim

  Spike, a RISC-V ISA Simulator

  Language:C2.4k130828822

• XUANTIE-RV/openc910

  OpenXuantie - OpenC910 Core

  Language:Verilog1.1k4527296

• geigi/cozy

  🎧 Listen to audio books 📚 on Linux

  Language:Python1.1k2939884

• chipsalliance/riscv-dv

  Random instruction generator for RISC-V processor verification

  Language:Python99382347323

• notAperson535/OneClick-macOS-Simple-KVM

  Tools to set up a easy, quick macOS VM in QEMU, accelerated by KVM. Works on Linux AND Windows.

  Language:Python60368250

• eclipse-embed-cdt/eclipse-plugins

  The Eclipse Embedded CDT plug-ins for Arm & RISC-V C/C++ developers (formerly known as the GNU MCU Eclipse plug-ins). Includes the archive of previous plug-ins versions, as Releases.

  Language:C55661489129

• riscvarchive/riscv-gcc

  35847209273

• pulp-platform/ara

  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

  Language:C35022180123

• OSCC-Project/iEDA

  Language:C++2944628

• riscv-non-isa/rvv-intrinsic-doc

  Language:C2795319689

• Gekkio/gb-research

  Game Boy hardware research

  Language:VHDL22410210

• efabless/openlane2

  The next generation of OpenLane, rewritten from scratch with a modular architecture

  Language:Python1881423835

• ESEO-Tech/emulsiV

  A visual simulator for teaching computer architecture using the RISC-V instruction set

  Language:JavaScript17241240

• hamsternz/Rudi-RV32I

  A rudimental RISCV CPU supporting RV32I instructions, in VHDL

  Language:VHDL11313016

• ncsu-eda/FreePDK3

  Language:Mathematica1087233

• ic-lab-duth/RISC-V-Vector

  Vector processor for RISC-V vector ISA

  Language:SystemVerilog1047024

• rejunity/tiny-asic-1_58bit-matrix-mul

  Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit

  Language:Verilog1011105

• taneroksuz/fpu

  IEEE 754 floating point library in system-verilog and vhdl

  Language:VHDL52239

• lightcode/8bit-computer

  A simple 8-bit computer build in Verilog.

  Language:Verilog39308

• the0b/MSP430-CORDIC-sine-cosine

  Language:C24225

• SymbioticEDA/nerv

  Naive Educational RISC-V -- A simple single-stage RV32I processor

  Language:SystemVerilog232

• Time0o/z80-verilog

  A Thoroughly Tested Verilog Implementation of a Z80 Compatible Processor Architecture

  Language:Verilog6300

• freecores/simple_pic

  Simple Programmable Interrupt Controller

  Language:Verilog4201

• spdy1895/RTL_synthesis_using_sky130

  Language:Verilog4103

• vojta7/aoc2020

  advent of code 2020

  Language:Rust1100