Nitcloud

Nitcloud's Stars

• parallax/jsPDF

  Client-side JavaScript PDF generation for everyone.

  Language:JavaScript28.7k4772.5k4.6k

• WZMIAOMIAO/deep-learning-for-image-processing

  deep learning for image processing including classification and object-detection etc.

  Language:Python21.6k1564077.8k

• peng-zhihui/Dummy-Robot

  我的超迷你机械臂机器人项目。

  Language:C11.6k3221732.6k

• espressif/esp32-camera

  Language:C1.8k57527617

• google/gemmlowp

  Low-precision matrix multiplication

  Language:C++1.8k11036450

• eugene-tarassov/vivado-risc-v

  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

  Language:Tcl77933196180

• BojanJurca/Esp32_oscilloscope

  ESP32 oscilloscope - see the signals through Web browser the way ESP32 sees them

  Language:C++738222984

• ucb-bar/gemmini

  Berkeley's Spatial Array Generator

  Language:Scala71729179145

• EEVengers/ThunderScope

  ThunderScope GitHub Repo

  Language:VHDL6573683148

• BRTResearch/AIChip_Paper_List

  541383110

• mike-lischke/vscode-antlr4

  ANTLR4 language support for Visual Studio Code

  Language:TypeScript4121721358

• circuitvalley/mipi_csi_receiver_FPGA

  MIPI CSI-2 Camera Sensor Receiver verilog HDL implementation For any generic FPGA. Tested with IMX219 on Lattice MachXO3LF. 2Gbps UVC Video Stream Over USB 3.0 with Cypress FX3. This is now Legacy Version!

  Language:C372241113

• lp6m/yolov5s_android

  Run yolov5s on Android device!

  Language:Java30392776

• jeanlemotan/esp32-cam-fpv

  esp32 cam digital low latency fpv

  Language:C++277133568

• Nic30/hdlConvertor

  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

  Language:C++2752213363

• WangXuan95/FPGA-ftdi245fifo

  FPGA-based USB fast data transmission using FT232H/FT600 chip. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。

  Language:Verilog23891474

• PacktPublishing/TinyML-Cookbook

  TinyML Cookbook, published by Packt

  Language:Jupyter Notebook22110663

• openasic-org/xk265

  xk265：HEVC/H.265 Video Encoder IP Core (RTL)

  Language:Verilog21218470

• abdelazeem201/ASIC-Design-Roadmap

  The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.

  Language:Verilog1726025

• adamgallas/fpga_accelerator_yolov3tiny

  Language:VHDL16524920

• 19801201/SpinalHDL_CNN_Accelerator

  CNN accelerator implemented with Spinal HDL

  Language:Scala1256333

• zslwyuan/AMF-Placer

  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM...)

  Language:C++8941118

• Nic30/d3-hwschematic

  D3.js and ELK based schematic visualizer

  Language:JavaScript8542513

• kholia/xvc-esp32

  Wireless JTAG 'cable' for Xilinx FPGAs. This is an 'English fork' of https://github.com/ciniml/xvc-esp32 project.

  Language:C++725017

• Infineon/wifi-host-driver

  Embedded Wi-Fi Host Driver that provides a set of APIs to interact with Cypress WLAN chips

  Language:C59241124

• SLAM-Hardware/acSLAM

  FPGA Hardware Implementation for SLAM

  Language:VHDL510310

• LSTM-Kirigaya/ComputerDesignExperiment

  计算机组成原理的实验，包括单周期CPU和五级流水线CPU的verilog实现

  Language:Verilog28114

• Rzfly/simple_riscv_soft_core

  This is a simple Risc-v core for software simulation on FPGA.

  Language:Verilog510

• nguyenhong-hoa/IEEE754-FPCalculator

  This repo will describe some module to calculate with Floating-Point 32 bit

  Language:Verilog210

• Flyingdog-Huang/slambook

  Language:C++1000