CS 256 Logic Design Lab Project
The aim of this project is to design and construct a simple processor in VHDL.
The processor is divided into four components - the control unit, the bus, latches and the arithmetic/logic unit (ALU). The latches are used as storage units for two 8-bit numbers. The ALU is designed to perform operations such as sum, difference, NAND, OR, XOR and inverse of two 8-bit numbers.
Project made by - Srijan Saini (180001056) and Aryan Verma (180001008)