Tairycy

Tairycy's Stars

• XUANTIE-RV/wujian100_open

  IC design and development should be faster，simpler and more reliable

  Language:Verilog1.9k14046573

• greatscottgadgets/luna

  Amaranth HDL framework for monitoring, hacking, and developing USB devices

  Language:Python99351115171

• ultraembedded/biriscv

  32-bit Superscalar RISC-V CPU

  Language:Verilog8682925148

• jbikker/lighthouse2

  Lighthouse 2 framework for real-time ray tracing

  Language:C++845432385

• ultravideo/kvazaar

  An open-source HEVC encoder

  Language:C84172281182

• THU-DSP-LAB/ventus-gpgpu

  GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

  Language:Scala635142874

• WangXuan95/FPGA-USB-Device

  An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed) device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。

  Language:Verilog6142822103

• CESNET/UltraGrid

  UltraGrid low-latency audio and video network transmission system

  Language:C5114029754

• GameTechDev/ISPCTextureCompressor

  ISPC Texture Compressor

  Language:C++442482599

• r9y9/pysptk

  A python wrapper for Speech Signal Processing Toolkit (SPTK).

  Language:Python441236379

• mv-lab/AISP

  AI Image SIgnal Processing and Computational Photography - Bokeh Rendering , Reversed ISP Challenge, Model-Based Image Signal Processors via Learnable Dictionaries. Official repo for NTIRE and AIM Challenges

  Language:Jupyter Notebook365152041

• ultraembedded/FPGAmp

  720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

  Language:C27018043

• openasic-org/xkISP

  xkISP：Xinkai ISP IP Core (HLS)

  Language:Verilog2511710106

• timvideos/HDMI2USB-litex-firmware

  A version of the HDMI2USB firmware based around LiteX tools produced by @Enjoy-Digital (based on misoc+migen created by @M-Labs)

  Language:Python1453127071

• yuqing-liu-dut/ISPLab

  An open-source image signal processing (ISP) pipeline implemented by C++

  Language:C++1312138

• Vidvox/hap-in-avfoundation

  A framework that allows AVFoundation to play back and record Hap video

  Language:Objective-C109263319

• WangXuan95/FPGA-Gzip-compressor

  An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). 基于FPGA的GZIP压缩器。输入原始数据，输出标准的GZIP格式，即常见的 .gz / .tar.gz 文件的格式。

  Language:Verilog1014523

• HuiiJi/ez_ISP

  This is a easy ISP (ez_ISP) for RAW to RGB conversion.

  Language:Python911110

• amaranth-farm/amlib

  assorted library of utility cores for amaranth HDL

  Language:Python816414

• tomverbeure/math

  SpinalHDL Hardware Math Library

  Language:Scala787414

• HuiiJi/AISP

  2D AI-NR model for raw images, including dataset、training、infer.

  Language:Python671422

• tomtor/HDL-deflate

  FPGA implementation of deflate (de)compress RFC 1950/1951

  Language:Verilog56576

• RayXie29/Chromatic_aberration_correction

  Implementation of "Removing chromatic aberration by digital image processing"

  Language:C++441017

• smvv/pybison

  Use Bison directly from Python

  Language:Python3771223

• Mithrilwoodrat/naivecompiler

  C compiler created in Python and LLVM

  Language:Python19301

• tomverbeure/usb_system

  SpinalHDL USB system for the ULPI based Arrow DECA board

  Language:Assembly19602

• UCLA-VAST/HT-Deflate-FPGA

  Language:Verilog14525

• ucb-ee290c/sp21-dma

  EE290C DMA

  Language:Scala71000

• Zeba-Xie/Open-USB2.0-Device-Controller

  USB2.0 Device Controller IP Core

  Language:Verilog7102

• CEA-Leti/naxriscv_doc

  5004