briansune
@briansune2pcb FPGA / ASIC Engineer HDL - Verilog / VHDL / Chisel Python/Scala Chisel STM32/STM8/AVR/PIC/WCH FPGA#Altera/Xilinx/Anlogic/AGM #USB PD3.1
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briansune's Stars
alexforencich/verilog-axi
Verilog AXI components for FPGA implementation
eugene-tarassov/vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
WangXuan95/FPGA-USB-Device
An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器,可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备,只需要3个FPGA普通IO,而不需要额外的接口芯片。
gatecat/CSI2Rx
Open Source 4k CSI-2 Rx core for Xilinx FPGAs
davidthings/tinyfpga_bx_usbserial
USB Serial on the TinyFPGA BX
Digilent/ZYBO
davemuscle/sigma_delta_converters
Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components