efabless/clear

Issues

• What CLEAR mean ?

  #36 opened 2 months ago by Martoni
  2

• IO PCB mapping

  #39 opened 3 months ago by Martoni
  0

• CLB schematic ?

  #37 opened 4 months ago by Martoni
  0

• Toolchain for firmware development

  #34 opened 5 months ago by benjaminSchilling33
  3

• Chaotic blinking flashing

  #35 opened 5 months ago by Martoni
  0

• How to syntesize and place & route for CLEAR ?

  #29 opened a year ago by Martoni
  1

• What is the current situation of clear eFPGA macro?

  #26 opened 2 years ago by WazaAbdulkadir
  4

• Wrong Defaults in 2304 tapeout

  #28 opened a year ago by marwaneltoukhy
  1

• Missing openfpga_arch2x2.xml

  #27 opened a year ago by muhammadusman7
  0

• simulation stuck while programing the fpga with some designs

  #19 opened 2 years ago by M0stafaRady
  2

• Remove old generated files from RTL-dev branch

  #18 opened 2 years ago by marwaneltoukhy
  0

• Location constraints in pin.cfg cause OpenLane flow to fail

  #3 opened 2 years ago by abdullahyildiz
  2

• PDK setup fails

  #7 opened 2 years ago by abdullahyildiz
  1

• Possible OpenLane version issue

  #5 opened 2 years ago by abdullahyildiz
  1

• How to run interactive mode for "fpga_core"

  #16 opened 2 years ago by msaideroglu
  0

• "synth_top.tcl" is missing

  #15 opened 2 years ago by msaideroglu
  0

• TapeOut: 2020-07 Unused power signal mismatch

  #14 opened 2 years ago by d-m-bailey
  2

• TapeOut: 2020-07 gpio_defaults_block not replaced in caravel.v

  #13 opened 2 years ago by d-m-bailey
  0

• TapeOut: 2020-07 Older version of simple_por layout

  #12 opened 2 years ago by d-m-bailey
  0

• TapeOut: 2020-07 Unconnected buffer inputs

  #11 opened 2 years ago by d-m-bailey
  0

• make setup fails

  #10 opened 2 years ago by abdullahyildiz
  0

• Fabric Netlist Reproducing

  #2 opened 3 years ago
  0