Having problem with synthesis when including my design as verilog blackbox

[AminSavari]

Hello,

I have my top module in verilog. I included it in RoccBlackBox.v which is in rocket_chip/src/main/resources/vsrc/. I also changed the configuration file Configs.scala in rocket_chip/src/main/scala/subsystem/. I changed the WithRoccExample class to this:

class WithRoccExample extends Config((site, here, up) => {
  case BuildRoCC => List(
   (p: Parameters) => {
      val blackbox = LazyModule(new BlackBoxExample(OpcodeSet.custom0, "RoccBlackBox")(p))
      blackbox
    })
})

then in vivado-riscv/src/main/scala/rocket.scala, I added this:

class Rocket64bb extends Config(
  new WithRoccExample() ++
  new WithNBreakpoints(8) ++
  new WithNBigCores(1)    ++
  new RocketBaseConfig)

When I try $make CONFIG=rocket64bb BOARD=vc707 bitstream I get:

ERROR: [Vivado 12-13638] Failed runs(s) : 'riscv_RocketChip_0_synth_1'
 'riscv_RocketChip_0_synth_1' run failed with below errors.
ERROR: [Synth 8-439] module 'RoccBlackBox' not found [/home/syn_dec/workspace/rocket64bb/system-vc707.v:90316]

ERROR: [Synth 8-6156] failed synthesizing module 'RocketTile' [/home/syn_dec/workspace/rocket64bb/system-vc707.v:88486]

ERROR: [Synth 8-6156] failed synthesizing module 'TilePRCIDomain' [/home//syn_dec/workspace/rocket64bb/system-vc707.v:93897]

ERROR: [Synth 8-6156] failed synthesizing module 'RocketSystem' [/home/syn_dec/workspace/rocket64bb/system-vc707.v:107672]

ERROR: [Synth 8-285] failed synthesizing module 'Rocket64bb' [/home/syn_dec/workspace/rocket64bb/rocket.vhdl:385]

ERROR: [Synth 8-6156] failed synthesizing module 'riscv_RocketChip_0' [/home/syn_dec/workspace/rocket64bb/vivado-vc707-riscv/vc707-riscv.gen/sources_1/bd/riscv/ip/riscv_RocketChip_0/synth/riscv_RocketChip_0.v:53]

ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

wait_on_runs: Time (s): cpu = 00:00:02 ; elapsed = 00:14:19 . Memory (MB): peak = 2627.676 ; gain = 0.000 ; free physical = 15210 ; free virtual = 25090
ERROR: [Common 17-39] 'wait_on_runs' failed due to earlier errors.

    while executing
"wait_on_run synth_1"
    (file "workspace/rocket64bb/vivado-vc707-riscv/make-synthesis.tcl" line 5)
make: *** [Makefile:313: workspace/rocket64bb/vivado-vc707-riscv/vc707-riscv.runs/synth_1/riscv_wrapper.dcp] Error 1

Then When I try to add the content of RoccBlackBox.v to system-vc707.v I get these warning:

WARNING: [IP_Flow 19-3664] IP 'riscv_RocketChip_0' generated file not found '/home/syn_dec/workspace/rocket64bb/vivado-vc707-riscv/vc707-riscv.gen/sources_1/bd/riscv/ip/riscv_RocketChip_0/riscv_RocketChip_0.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'riscv_RocketChip_0' generated file not found '/home/syn_dec/workspace/rocket64bb/vivado-vc707-riscv/vc707-riscv.gen/sources_1/bd/riscv/ip/riscv_RocketChip_0/riscv_RocketChip_0_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'riscv_RocketChip_0' generated file not found '/home//workspace/rocket64bb/vivado-vc707-riscv/vc707-riscv.gen/sources_1/bd/riscv/ip/riscv_RocketChip_0/riscv_RocketChip_0_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'riscv_RocketChip_0' generated file not found '/home/syn_dec/workspace/rocket64bb/vivado-vc707-riscv/vc707-riscv.gen/sources_1/bd/riscv/ip/riscv_RocketChip_0/riscv_RocketChip_0_sim_netlist.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'riscv_RocketChip_0' generated file not found '/home/zc707/syn_dec/workspace/rocket64bb/vivado-vc707-riscv/vc707-riscv.gen/sources_1/bd/riscv/ip/riscv_RocketChip_0/riscv_RocketChip_0_sim_netlist.vhdl'. Please regenerate to continue.

which will result to a failed synthesis. Could you please tell me why RoccBlackBox.v is not automatically included in system-vc707.v and what I am doing wrong?

[eugene-tarassov]

Additional Verilog sources, like RoccBlackBox.v, are supposed to be added to Vivado project file, not to system-vc707.v, which is generated from Chisel. The project file is created by vivado.tcl script. You can modify the script to include more Verilog files.