hzeller

hzeller's Stars

• ManimCommunity/manim

  A community-maintained Python framework for creating mathematical animations.

  Language:Python19.7k1341.5k1.5k

• ArthurSonzogni/FTXUI

  :computer: C++ Functional Terminal User Interface. :heart:

  Language:C++6.3k66319390

• cue-lang/cue

  The home of the CUE language! Validate and define text-based and dynamic configuration

  Language:Go4.8k432.3k278

• google/skywater-pdk

  Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

  Language:Python2.9k149267376

• clasp-developers/clasp

  clasp Common Lisp environment

  Language:Common Lisp2.5k100807140

• rtomayko/ronn

  the opposite of roff

  Language:Ruby1.4k288082

• lowRISC/ibex

  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

  Language:SystemVerilog1.3k96809488

• google/xls

  XLS: Accelerated HW Synthesis

  Language:C++1.1k621.2k166

• theacodes/kicanvas

  The KiCAD web viewer

  Language:TypeScript550138222

• machineagency/jubilee

  jubilee source files; for the docs, see:

  Language:GAP54883175112

• thedalles77/USB_Laptop_Keyboard_Controller

  Details for building a USB keyboard and touchpad controller from an old laptop.

  Language:C++382261766

• jamieiles/80x86

  80186 compatible SystemVerilog CPU core and FPGA reference design

  Language:C++36526751

• chipsalliance/Surelog

  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

  Language:C++3362791267

• chipsalliance/sv-tests

  Test suite designed to check compliance with the SystemVerilog standard.

  Language:SystemVerilog2621827669

• chipsalliance/Cores-VeeR-EL2

  VeeR EL2 Core

  Language:SystemVerilog229247368

• bilibili/quiche

  Language:C++194161943

• chipsalliance/synlig

  SystemVerilog support for Yosys

  Language:Verilog1411423320

• tinyvision-ai-inc/pico-ice

  Raspberry Pi PICO board + Lattice iCE40 FPGA's

  Language:HTML133111023

• yne/vcd

  VCD file (Value Change Dump) command line viewer

  Language:C1057812

• pieter3d/simview

  Language:C++774117

• abnoname/iceZ0mb1e

  FPGA 8-Bit TV80 SoC for Lattice iCE40 with complete open-source toolchain flow using yosys and SDCC

  Language:Verilog529716

• jirutka/otf2bdf

  OpenType to BDF Converter (unofficial mirror)

  Language:C464015

• thestumbler/vectorscope-kicad

  Making a complete KiCad Project from the Hackaday Supercon 2023 Vectorscope Badge

  160

• jmillikin/rules_bison

  Bazel build rules for GNU Bison

  Language:Starlark154623

• jmillikin/rules_flex

  Bazel build rules for Flex

  Language:Starlark15375

• jmillikin/rules_m4

  Bazel build rules for GNU M4

  Language:Starlark154911

• mntmn/fomu-vga

  Language:Verilog13300

• jazvw/chip_art

  Convert an image to a GDS format for inclusion in a zerotoasic project

  Language:Python12121

• yesco/minimalisp

  Language:C7200

• squeed/bfon

  Bowl Full of Nouns - the Web version

  Language:TypeScript3410