jack-1988

jack-1988's Stars

• 996icu/996.ICU

  Repo for counting stars and contributing. Press F to pay respect to glorious developers.

  270k4.2k021.1k

• justjavac/free-programming-books-zh_CN

  :books: 免费的计算机编程类中文书籍，欢迎投稿

  112k5.9k028.3k

• MisterBooo/LeetCodeAnimation

  Demonstrate all the questions on LeetCode in the form of animation.（用动画的形式呈现解LeetCode题目的思路）

  Language:Java75.6k2.5k6114k

• wangzheng0822/algo

  数据结构和算法必知必会的50个代码实现

  Language:Python23k8311267.1k

• egonSchiele/grokking_algorithms

  Code for the book Grokking Algorithms (https://www.amazon.com/dp/1633438538)

  Language:JavaScript11.9k321513.8k

• lawlite19/MachineLearning_Python

  机器学习算法python实现

  Language:Python7.4k246202.4k

• YosysHQ/picorv32

  PicoRV32 - A Size-Optimized RISC-V CPU

  Language:Verilog3.2k167177766

• SI-RISCV/e200_opensource

  Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

  Language:Verilog2.6k229431k

• lowRISC/opentitan

  OpenTitan: Open source silicon root of trust

  Language:SystemVerilog2.6k1066.9k792

• darklife/darkriscv

  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  Language:Verilog2.2k9440291

• XUANTIE-RV/wujian100_open

  IC design and development should be faster，simpler and more reliable

  Language:Verilog1.9k14046573

• nvdla/hw

  RTL, Cmodel, and testbench for NVDLA

  Language:Verilog1.8k167347572

• corundum/corundum

  Open source FPGA-based NIC and platform for in-network compute

  Language:Verilog1.8k88176427

• analogdevicesinc/hdl

  HDL libraries and projects

  Language:Verilog1.6k159901.5k

• progranism/Open-Source-FPGA-Bitcoin-Miner

  A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.

  Language:VHDL1.3k20831553

• alexforencich/verilog-pcie

  Verilog PCI express components

  Language:Verilog1.2k5251307

• yidao620c/core-algorithm

  算法集锦的python实现

  Language:Python776563278

• alexforencich/verilog-i2c

  Verilog I2C interface for FPGA implementation

  Language:Verilog562369174

• MisterBooo/Article

  十大经典排序算法动画，看我就够了！

  529167124

• alexforencich/verilog-uart

  Verilog UART

  Language:Verilog4292410129

• gycg/Algorithm

  算法导论python实现

  Language:Python373110119

• OpenDLA/OpenDLA

  A discussion group on Open Source Deep Learning Accelerator, with technical reports and potential hardware/software issues.

  13842039

• alexforencich/verilog-dsp

  Verilog digital signal processing components

  Language:Python1168138

• freecores/ethmac

  Ethernet MAC 10/100 Mbps

  Language:Verilog797234

• Martoni/pcie_debug

  Command line tool to Read/Write to PCIe BARx memory space

  Language:C696136

• alexforencich/python-ivi

  A Python implementation of the Interchangeable Virtual Instrument standard.

  Language:Python5511014

• Tommydag/CAN-Bus-Controller

  An CAN bus Controller implemented in Verilog

  Language:Verilog435325

• csus-senior-design/i2c

  I2C Master and Slave

  Language:Verilog296012

• senior-design-team25/CAN_module

  CAN Verilog HDL module implementation

  Language:VHDL1302

• soareswallace/CANDecoder

  Language:Verilog1102