/VerilogBasics

Basics of Verilog implementation

Primary LanguageSystemVerilogMIT LicenseMIT

Verilog_Basics_With_Examples

This Basics of verilog Basics Repo course includes;

  • Understanding Levels of Abstraction in Digital Design
  • Types of Modelling (Gate Level, Data Flow & Behaviour) &
  • Execution Flow of Verilog code(TestBench Vs Design)

** Resources Files contains the examples of the online compiler and simulator found here