midnighter95's Stars
jlevy/the-art-of-command-line
Master the command line, in one page
chipsalliance/chisel
Chisel: A Modern Hardware Design Language
riscv/riscv-isa-manual
RISC-V Instruction Set Manual
seisman/how-to-write-makefile
跟我一起写Makefile重制版
chipsalliance/rocket-chip
Rocket Chip Generator
com-lihaoyi/Ammonite
Scala Scripting
verilator/verilator
Verilator open-source SystemVerilog simulator and lint system
riscv-software-src/riscv-isa-sim
Spike, a RISC-V ISA Simulator
com-lihaoyi/mill
Mill is a fast JVM build tool that supports Java and Scala. 2-4x faster than Gradle and 5-10x faster than Maven for common workflows, Mill aims to make your project’s build process performant, maintainable, and flexible
lowRISC/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
freechipsproject/chisel-bootcamp
Generator Bootcamp Material: Learn Chisel the Right Way
com-lihaoyi/os-lib
OS-Lib is a simple, flexible, high-performance Scala interface to common OS filesystem and subprocess APIs
gtkwave/gtkwave
GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.
NJU-ProjectN/ics-pa-gitbook
riscv/riscv-debug-spec
Working Draft of the RISC-V Debug Specification Standard
riscv-collab/riscv-openocd
Fork of OpenOCD that has RISC-V support
NJU-ProjectN/nvboard
NJU Virtual Board
plctlab/weloveinterns
PLCT实验室实习生社区。
chipsalliance/playground
chipyard in mill :P
agile6v/scala-tutorials
sequencer/arithmetic