mit-ll/CEP

Modifying the CORES

Iripi97 opened this issue · 7 comments

Iripi97 commented

I was just trying to experiment with the size of the CEP (remove a core). I tried removing the AES core and running CEP after generating the new bitstream and memory configuration file but it is failing to run all the tests now. Is this expected behavior? (Side note: I did not remake the bbl.bin file)

I only removed the instantiations for the AES module in the main Verilog file generated from the Chisel.

Any response would be greatly appreciated.

bchetwynd commented

You'll need to update ./cosim/drivers/cep_tests/cep_srot.cc under the function LLKI_Setup to remove the following statement:

  • DisableLLKI(AES_BASE_K ); EnableLLKI(AES_BASE_K );

Rebuild Linux and run cep_diag as you did before.

Iripi97 commented

@bchetwynd Thank you for the suggestion. After making the modifications you described the CEP tests for each core are passing.

I was wondering... the following tests still fail (they fail because they lock the VC707 up into a frozen state where it has to be reset to be used again):
11. cepSrotErrTest
12. cepAccessTest
20. cepRegTest
21. cepMacroBadKey
22. cepMacroMix
23. cepMultiThread
24. cepSrotMaxKeyTest
Is this expected behavior when removing one of the cores? (Side note: cep_AES failed as well, but this was expected since the core was removed).

dralabeing commented

Hi, Are there additional documentation or examples of CEP integration into other SoCs? We are trying to evaluate and potentially integrate CEP into our flow described here: https://github.com/The-OpenROAD-Project/

Any such information will be highly appreciated.

Thanks in advance.

bchetwynd commented

Unfortunately, there is no documentation available other than what is in this repository. I will note that both the current CEP and future versions are a mix of System Verilog, Verilog and Chisel generated verilog. I am uncertain how that fits into your flow.

I presume you are familiar with UC Berkeley's work on Chipyard?

dralabeing commented

Thanks @bchetwynd, We only support Verilog at the moment. Thanks for the link to Chipyard. No I wasn't familiar-will take a look

bchetwynd commented

@dralabeing - They seem have similar mission to your OpenROAD project. Good luck.

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dralabeing commented

@dralabeing - They seem have similar mission to your OpenROAD project. Good luck.

@bchetwynd We are already engaged with Chipyard (I wasn't aware of that). Thanks for your help.