Error while compiling the xilinx simulation libraries
Rahul-Kande opened this issue · 5 comments
Hello,
I am trying to setup the CEP SoC and run the bareMetalTests/regTest from the cosim. But, I am getting the following error when I run the vivado tcl command: compile_simlib -simulator modelsim -simulator_exec_path {/opt/questa-2019.1/questasim/bin} -family all -language all -library all -dir {./xil_lib} -force -verbose (Note that I had to change the original -simulator questa to -simulator modelsim since otherwise I was getting an error saying 'questa executable' not found) .
The log with the error is attached here:
cep_error.log.txt
Note: My system details:
OS: 64-bit CentOS
Modelsim: Model Technology ModelSim SE-64 vsim 10.7 Simulator 2017.12 Dec 6 2017
Vivado: Vivado v2017.4 (64-bit)
SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
Here is everything I did before:
--> cloned CEP
--> did ./get_external_dependencies.sh all
--> installed the riscv-toolchain: ./build.sh
--> set all the variables: RISCV, PATH
--> generated the dft/idft/FIR/IIR cores
--> built the hardware: make -f Makefile.vc707-u500devkit verilog and make -f Makefile.vc707-u500devkit mcs
--> set the variables VIVADO_PATH, SIMULATOR_PATH, RISCV_DIR
We noticed during development that not all tool versions yielded positive results.
For reference, these are the versions we validated the design against:
Modelsim Questa Sim-64 v2019.1 (for co-simulation)
Xilinx Vivado 2018.3 (Design or System Edition
I'd recommend using those versions if possible. Otherwise, I would double check that your version of QuestaSim & Vivado are compatible.
Hello,
Thank you for the early reply. I do understand that I am not having the exact versions as recommended. But, being a student, I only get access to what my university IT provides. So, I have very little choice here.
What I would like to know is if it will be possible to run the SoC with the software available for me.
When I try to 'make' in the bareMetalTests/regTest directory, I get the following errors:
** Error: /home/grads/r/rahulkande/thesis/rocket_chip/CEP/hdl_cores/freedom/builds/vc707-u500devkit/obj/ip/corePLL/corePLL_clk_wiz.v(137): Module 'MMCME2_ADV' is no
t defined.
** Error: /home/grads/r/rahulkande/thesis/rocket_chip/CEP/hdl_cores/freedom/builds/vc707-u500devkit/obj/ip/corePLL/corePLL_clk_wiz.v(186): Module 'BUFG' is not defi
ned.
** Error: /home/grads/r/rahulkande/thesis/rocket_chip/CEP/hdl_cores/freedom/builds/vc707-u500devkit/obj/ip/corePLL/corePLL_clk_wiz.v(195): Module 'BUFG' is not defi
ned.
** Error: /home/grads/r/rahulkande/thesis/rocket_chip/CEP/cosim/dvt/behav_models/VCShell_bare.v(466931): Module 'IBUFDS' is not defined.
-- Loading module IBuf
-- Loading module IBuf
-- Loading module IBuf
** Error: /home/grads/r/rahulkande/thesis/rocket_chip/CEP/cosim/dvt/behav_models/VCShell_bare.v(466936): Module 'IBUF' is not defined.
-- Loading module PowerOnResetFPGAOnly
Optimization failed
End time: 00:17:51 on May 05,2020, Elapsed time: 0:00:02
Errors: 12, Warnings: 0
make: *** [/home/grads/r/rahulkande/thesis/rocket_chip/CEP/cosim/bareMetalTests/bareMetalTests_work/_info] Error 2
Do you think this error is because I failed to compile the Xilinx simulation libraries?
@Rahul-Kande - Those errors are definitely because of the failed compile for the Xilinx simulation libraries. I also appreciate that not all tool versions are available.
Unfortunately, the best advice I can offer is to reach out to your University's IT department and see if other versions are available. If you cannot get the ones I specified, then you could try playing with permuting the versions of tools you have access to. Our build does not require every component in every library to be compiled. There may be a combination that works for you.
The CEP uses several Xilinx specific components in addition to the ones listed in the errors above.
Ok, thank you. I'll try that and get back in case I need help.
I have tried with the recommended version and am able to run the tests without errors.
So, closing the issue.
Thank you for your assistance.