Switching to User privilege level
Rahul-Kande opened this issue · 2 comments
Hello,
I am simulating the SoC in bare-metal mode and trying to switch to the user privilege level.
This is the code I am using:
` if (cpuId == 0) {
uint64_t curr_pc ;
asm volatile ( "auipc %0, 0x0 \n\t"
: "=r"(curr_pc) );
curr_pc = curr_pc + 24 ;
asm volatile ( "csrw mepc, %0 \n\t"
:
: "r"(curr_pc) );
uint64_t x = 0x00001800 ;
asm volatile ( "csrc mstatus, %0 \n\t"
:
: "r"(x) );
asm volatile ( "mret \n\t" );
`
But, I get the following assertion violation in the trace when I run this program:
`C0: 4158 [1][0] pc=[0080001048] W[r15=0000000080001048][1] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[00000797] [05] [0000000000] [3]
C0: 4159 [1][0] pc=[008000104c] W[r15=0000000080001060][1] R[r15=0000000080001048] R[r24=0000000000000003] inst=[000007e1] [05] [0000000000] [3]
C0: 4160 [1][0] pc=[008000104e] W[r 0=ffffffc6632117c6][1] R[r15=0000000080001060] R[r 1=0000000000000003] inst=[34179073] [05] [0000000000] [3]
C0: 4161 [1][0] pc=[0080001052] W[r15=0000000000002000][1] R[r 0=0000000080001060] R[r 0=0000000000000003] inst=[00006789] [05] [0000000000] [3]
C0: 4162 [1][0] pc=[0080001054] W[r15=0000000000001800][1] R[r15=0000000000002000] R[r 0=0000000000000000] inst=[80078793] [05] [0000000000] [3]
C0: 4163 [1][0] pc=[0080001058] W[r 0=8000000a00007800][1] R[r15=0000000000001800] R[r 0=0000000000000000] inst=[3007b073] [05] [0000000000] [3]
C0: 4164 [0][0] pc=[0080001058] W[r 0=8000000a00006000][0] R[r15=0000000000000000] R[r 0=0000000000000003] inst=[3007b073] [05] [0000000000] [3]
C0: 4165 [0][0] pc=[0080001058] W[r 0=8000000a00006000][0] R[r15=0000000000000000] R[r 0=0000000000000000] inst=[3007b073] [05] [0000000000] [3]
C0: 4166 [0][0] pc=[0080001058] W[r 0=8000000a00006000][0] R[r15=0000000000000000] R[r 0=0000000000000000] inst=[3007b073] [05] [0000000000] [3]
C0: 4167 [0][0] pc=[0080001058] W[r 0=8000000a00006000][0] R[r15=0000000000000000] R[r 0=0000000000000000] inst=[3007b073] [05] [0000000000] [3]
C0: 4168 [1][0] pc=[008000105c] W[r 0=4cc995994cc99599][0] R[r 0=0000000000000000] R[r 2=0000000000000003] inst=[30200073] [05] [0000000000] [3]
C0: 4169 [0][0] pc=[008000105c] W[r 0=4cc995994cc99599][0] R[r 0=0000000000000000] R[r 2=0000000000000000] inst=[30200073] [05] [0000000000] [0]
C0: 4170 [0][0] pc=[008000105c] W[r 0=4cc995994cc99599][0] R[r 0=0000000000000000] R[r 2=0000000000000000] inst=[30200073] [05] [0000000000] [0]
C0: 4171 [0][0] pc=[008000105c] W[r 0=4cc995994cc99599][0] R[r 0=0000000000000000] R[r 2=0000000000000000] inst=[30200073] [05] [0000000000] [0]
C0: 4172 [0][0] pc=[008000105c] W[r 0=4cc995994cc99599][0] R[r 0=0000000000000000] R[r 2=0000000000000000] inst=[30200073] [05] [0000000000] [0]
C0: 4173 [0][0] pc=[008000105c] W[r 0=4cc995994cc99599][0] R[r 0=0000000000000000] R[r 2=0000000000000000] inst=[30200073] [05] [0000000000] [0]
C0: 4174 [0][0] pc=[008000105c] W[r 0=4cc995994cc99599][0] R[r 0=0000000000000000] R[r 2=0000000000000000] inst=[30200073] [05] [0000000000] [0]
C0: 4175 [0][0] pc=[008000105c] W[r 0=4cc995994cc99599][0] R[r 0=0000000000000000] R[r 2=0000000000000000] inst=[30200073] [05] [0000000000] [0]
C0: 4176 [0][0] pc=[008000105c] W[r 0=4cc995994cc99599][0] R[r 0=0000000000000000] R[r 2=0000000000000000] inst=[30200073] [05] [0000000000] [0]
C0: 4177 [0][0] pc=[008000105c] W[r 0=4cc995994cc99599][0] R[r 0=0000000000000000] R[r 2=0000000000000000] inst=[30200073] [05] [0000000000] [0]
Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Frontend.scala:341:21)
at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), "'A' channel carries Get type unsupported by manager" + extra)
Note: The trace format is a little different, but I don't think that should be an issue ( printf("C%d: %d [%d][%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] [%x] [%x] [%d]\n", coreMonitorBundle.hartid, coreMonitorBundle.time, coreMonitorBundle.valid, csr.io.trace(0).exception, coreMonitorBundle.pc, coreMonitorBundle.wrdst, coreMonitorBundle.wrdata, coreMonitorBundle.wren, coreMonitorBundle.rd0src, coreMonitorBundle.rd0val, coreMonitorBundle.rd1src, coreMonitorBundle.rd1val, coreMonitorBundle.inst, csr.io.trace(0).cause, csr.io.trace(0).tval, csr.io.status.prv ))
`
This is being processed within the rocket-chip (https://github.com/chipsalliance/rocket-chip.git) of which the CEP uses a fairly old version (Oct 2018). While we have plans to upgrade, I cannot estimate exactly when that will occur.
I suggest looking into the rocket-chip repo to see if there is any info on the issue you are seeing.
Rocket Chip upgrade with CEP v2.6 release in September 2020. I don't know if you are still working on this effort, but it would be good to hear if the problem is gone now.