rubinsteina13
Embedded C/C++, Verilog/VHDL RTL (DSP/IP Cores) Design, Hardware, Digital & Analog Electronics, Power Electronics & Electric Drive
Individual EntrepreneurSlavutych, Ukraine
Pinned Repositories
C_INDUCTION_MOTOR_ESTIMATORS_LIB
C-library with implementation of the Induction Motor rotor speed anf flux estimators (observers)
C_PID_CONTROLLERS_LIB
C-library with floating point P, PI, PD, PID-controllers implementation
C_SPACE_VECTOR_TRANSFS_LIB
C-library with various space-vector transformation implementations
C_SVPWM_LIB
C-library with implementation of the Space-Vector PWM generation technique
SV_CLARKE_TRANSFORMATION_CORES
Synthesizable SystemVerilog IP-Cores of the Forward and Backward Clarke Transformation
SV_DSM_CORE
Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator
SV_I2S_RX_CORE
Synthesizable SystemVerilog IP-Core of the I2S Receiver
yafpgatetris
Yet Another Tetris on FPGA Implementation
rubinsteina13's Repositories
rubinsteina13/C_SVPWM_LIB
C-library with implementation of the Space-Vector PWM generation technique
rubinsteina13/C_INDUCTION_MOTOR_ESTIMATORS_LIB
C-library with implementation of the Induction Motor rotor speed anf flux estimators (observers)
rubinsteina13/C_PID_CONTROLLERS_LIB
C-library with floating point P, PI, PD, PID-controllers implementation
rubinsteina13/SV_I2S_RX_CORE
Synthesizable SystemVerilog IP-Core of the I2S Receiver
rubinsteina13/C_SPACE_VECTOR_TRANSFS_LIB
C-library with various space-vector transformation implementations
rubinsteina13/SV_CLARKE_TRANSFORMATION_CORES
Synthesizable SystemVerilog IP-Cores of the Forward and Backward Clarke Transformation
rubinsteina13/SV_DSM_CORE
Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator
rubinsteina13/yafpgatetris
Yet Another Tetris on FPGA Implementation