saahm

saahm's Stars

• agra-uni-bremen/microrv32

  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype

  Language:Scala425

• meiniKi/FazyRV

  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

  Language:SystemVerilog734

• SpinalHDL/SpinalWorkshop

  Labs to learn SpinalHDL

  Language:Scala14439

• ehw-fit/py-paretoarchive

  Python Pareto archive

  Language:C++31

• tomverbeure/math

  SpinalHDL Hardware Math Library

  Language:Scala7814

• actualbudget/actual

  A local-first personal finance app

  Language:TypeScript15.6k1.2k

• riscv/learn

  Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

  57168

• andreasWallner/VexiiRiscv

  1

• JulianKemmerer/PipelineC

  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

  Language:Python60249

• YosysHQ/yosys

  Yosys Open SYnthesis Suite

  Language:C++3.5k894

• agra-uni-bremen/symex_processor_verification

  Language:C++53

• SpinalHDL/NaxRiscv

  Language:Scala26940

• ehw-fit/ariths-gen

  Generator of arithmetic circuits (multipliers, adders) and approximate circuits

  Language:C283

• SpinalHDL/rvls

  RISCV lock-step checker based on Spike

  Language:C++81

• riscv/riscv-fast-interrupt

  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)

  Language:Makefile24749

• cocotb/cocotb

  cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

  Language:Python1.8k512

• scale-lab/DRiLLS

  DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)

  Language:Python10233

• speeduino/speeduino

  Speeduino - Arduino based engine management

  Language:C++1.4k558

• maikmerten/hx8k-sram16-extension

  A PCB with 4 Mbit of SRAM, two LEDs, a button, SPI-Flash, SPI-connectors, and a single-row pmod-compatible connector for the Lattice HX8K Breakout Board

  41

• saahm/hx8k-sram16-extension

  A PCB with 4 Mbit of SRAM, two LEDs, a button, SPI-Flash, SPI-connectors, and a single-row pmod-compatible connector for the Lattice HX8K Breakout Board

  1

• maikmerten/hx8k-breakout-extension

  A PCB with SRAM, buttons, LEDs and some pmod-compatible connectors for the Lattice HX8K Breakout Board

  104

• SyedAnasAlam/Ice-Board

  A PCB for the Lattice ICE40 FPGA

  1

• icebreaker-fpga/icebreaker

  Small and low cost FPGA educational and development board

  57775

• mattvenn/first-fpga-pcb

  FPGA dev board based on Lattice iCE40 8k

  Language:Verilog6515

• stnolting/neorv32

  :desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

  Language:VHDL1.6k227

• proteus-core/proteus

  The SpinalHDL design of the Proteus core, an extensible RISC-V core.

  Language:Scala4210

• toddmaustin/bringup-bench

  Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, accelerators, compilers and operating systems. You probably don't need Bringup-Bench, but if you do, you probably need it badly!

  Language:C12317

• ics-jku/wal

  WAL enables programmable waveform analysis.

  Language:Python13818

• jjyy-Huang/SpinalHDL-ethernet

  Language:Scala151

• amahzoon/genmul

  Language:C++142