thuvasooriya

thuvasooriya's Stars

• alexandresanlim/Badges4-README.md-Profile

  :octocat: Improve your README.md profile with these amazing badges.

  Language:Markdown10.8k461471.6k

• huggingface/lerobot

  🤗 LeRobot: Making AI for Robotics more accessible with end-to-end learning

  Language:Python8.2k84166847

• rothgar/awesome-tmux

  A list of awesome resources for tmux

  8k12011311

• riscv/riscv-isa-manual

  RISC-V Instruction Set Manual

  Language:TeX3.8k211938660

• openhwgroup/cva6

  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

  Language:Assembly2.3k941.1k707

• saicaca/fuwari

  ✨A static blog template built with Astro.

  Language:Astro1.7k18148388

• m-labs/migen

  A Python toolbox for building complex digital hardware

  Language:Python1.2k65132211

• espressif/esp-at

  AT application for ESP32/ESP32-C2/ESP32-C3/ESP32-C6/ESP8266

  Language:C93853811860

• riscv-software-src/riscv-tests

  Language:C92378240477

• pulp-platform/pulpino

  An open-source microcontroller system based on RISC-V

  Language:C91787393300

• jess-moss/koch-v1-1

  A version 1.1 of the Alexander Koch low cost robot arm with some small changes.

  508102045

• openhwgroup/cvfpu

  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

  Language:SystemVerilog4493864117

• sysprog21/rv32emu

  Compact and Efficient RISC-V RV32I[MAFC] emulator

  Language:C43225141105

• markhorn-dev/astro-nano

  Astro Nano is a static, minimalist, lightweight, lightning fast portfolio and blog.

  Language:Astro41727154

• m-labs/misoc

  The original high performance and small footprint system-on-chip based on Migen™

  Language:C315427886

• RoaLogic/RV12

  RISC-V CPU Core

  Language:SystemVerilog301211552

• Xilinx/XilinxVirtualCable

  Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or SoC design without using a physical cable.

  Language:C23031983

• juspay/nixos-unified-template

  A multi-platform Nix configuration template optimized as development environment, based on nixos-unified.

  Language:Nix194123145

• arduino/nina-fw

  Firmware for u-blox NINA W102 WiFi/BT module

  Language:C1382551116

• csnol/STM32-OTA

  STM32-OTA on Arduino IDE

  Language:C++12610757

• tmbinc/xvcd

  Xilinx Virtual Cable Daemon

  Language:C11218261

• rsnikhil/Forvis_RISCV-ISA-Spec

  Formal specification of RISC-V Instruction Set

  Language:Haskell9818319

• AngeloJacobo/RISC-V

  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

  Language:Verilog75715

• jedrzejboczar/nvim-dap-cortex-debug

  Extension for nvim-dap providing integration with VS Code's cortex-debug

  Language:Lua40284

• IOES-Lab/ROS2_Jazzy_MacOS_Native_AppleSilicon

  Language:Shell28242

• ahmad-mirsalari/PULP

  A public repository discussing the PULP (Parallel Ultra Low Power) platform for open-source RISC-V processors and associated software.

  17302

• pulp-platform/banshee

  Language:Rust17486

• FPGAsm/FPGAsm

  A low-level hierarchical netlist assembler for FPGAs

  Language:C++11202

• npalmer5620/razor_cpu

  RISC-V RV32I CPU core in SystemVerilog

  Language:SystemVerilog20

• MrFriis/RV32I-Simulator

  Simple simulator for the RISC-V 32I base instruction set

  Language:C++10