z1skgr/reconf-Computing__HLS

High Level synthesis of data transfer in Vivado, Vivado HLS

reconfigurable Computing

Designing Protocol Processing Systems with Vivado High-Level Synthesis

Parts

• 64-FIFO Implementantion 32 bits words
• Data flow-system implementation
• 64-FIFO and Data flow-system in a integrated design

Setup

Vivado 2017.4 and Vivado HLS 2017.4 Xilinx®

To run the project: Install Vivado 2017.4 HL design edition (full version)

• SoC -> Zynq 7000

Acknowledgement

This project was created for the requirements of the lesson Reconfigurable Programming/Computing.