/FPGA_Slot_Machine

A slot machine created in System Verilog. It was built, simulated, synthesized, and implemented in Vivado, for use on the Xilinx Basys 3 board.

Primary LanguageSystemVerilog

FPGA_Slot_Machine(Top level design in Toplevel.sv)

A slot machine created in System Verilog. It was built, simulated, synthesized, and implemented in Vivado, on the Xilinx Basys 3 board.

This is my final project for my first Digital Design class as a freshman EE at Cal Poly.

I enjoyed the class a lot, and can picture myself doing more stuff like this for a career.