JorisPellereau

JorisPellereau's Stars

• riscv-collab/riscv-gnu-toolchain

  GNU toolchain for RISC-V, including GCC

  Language:C3.6k1421.1k1.2k

• alexforencich/verilog-ethernet

  Verilog Ethernet components for FPGA implementation

  Language:Verilog2.4k118170708

• stnolting/neorv32

  :desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

  Language:VHDL1.6k51209229

• alexforencich/verilog-axi

  Verilog AXI components for FPGA implementation

  Language:Verilog1.5k5374461

• trabucayre/openFPGALoader

  Universal utility for programming FPGA

  Language:C++1.2k38236266

• alexforencich/verilog-pcie

  Verilog PCI express components

  Language:Verilog1.2k5251304

• jgraph/drawio-libs

  Libraries for draw.io

  1k3611372

• alexforencich/verilog-axis

  Verilog AXI stream components for FPGA implementation

  Language:Python7504724229

• getting-things-gnome/gtg

  Getting Things GNOME! desktop app development

  Language:Python56126734165

• taichi-ishitani/tvip-axi

  AMBA AXI VIP

  Language:SystemVerilog3641639106

• Xilinx/XilinxTclStore

  Xilinx Tcl Store

  Language:Tcl3496429188

• StefanSchippers/xschem

  A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

  Language:C3411723521

• funningboy/uvm_axi

  uvm AXI BFM(bus functional model)

  Language:Verilog233204113

• xesscorp/VHDL_Lib

  Library of VHDL components that are useful in larger designs.

  Language:VHDL22920468

• stnolting/neoTRNG

  🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

  Language:VHDL1746120

• execuc/LCInterlocking

  FreeCAD module to create laser cut interlocking parts.

  Language:Python144135333

• ogamespec/ogame-opensource

  This is revived OGame v 0.84 with old design.

  Language:PHP96913746

• modded-factorio/bobsmods

  Factorio mods by Bobingabout

  Language:Lua65716132

• wavedrom/cli

  CLI for WaveDrom

  Language:JavaScript6171912

• efabless/clear

  Language:Verilog5810247

• int-main/Quine-McCluskey

  Implementation of Quine McCluskey algorithm in Python 3

  Language:Python562519

• nandland/getting-started-with-fpgas

  Verilog and VHDL for book

  Language:VHDL566414

• yuri-panchul/systemverilog-homework

  SystemVerilog language-oriented exercises

  Language:SystemVerilog547273

• MahmouodMagdi/Clock-Domain-Crossing-Synchronizers

  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference for understanding and implementing robust clock domain crossing solutions in digital systems.

  Language:Verilog48304

• fredrequin/verilator_xilinx

  Re-coded Xilinx primitives for Verilator use

  Language:Verilog41413

• themperek/cocotb-vivado

  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.

  Language:Python33715

• oceanBigOne/MajorityJudgment

  Php class for Majority Judgment

  Language:PHP17881

• raczben/pysct

  Python wrapper for Xilinx's XSCT/XSDB console

  Language:Python6215

• Avilad0/Socket_Audio_Streaming_usingPython

  Audio Streaming on localhost or internet using Python Socket Programming

  Language:Python4101

• olofk/Booth_Multipliers

  Parameterized Booth Multiplier in Verilog 2001

  Language:Verilog1101